Radiation-Hardened Memory Circuit with EDAC and Segmented Scrubbing
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Solution Overview
Problem
CMOS integrated circuits operating in extreme environments, such as those exposed to radiation, temperature variations, and voltage fluctuations, experience increased sensitivity to 'soft errors' leading to unreliable operation due to single-bit failures and logic network failures, making error-free operation nearly impossible.
Innovation Solution
A memory circuit incorporating error detection and correction (EDAC) methods, including parity checking, EDAC encoding, and periodic scrubbing, along with radiation-hardened process isolation (RHPI) schemes like buried guard rings (BGR) and parasitic isolation devices (PID), to reduce sensitivity to radiation and prevent single-event upsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If radiation hardening techniques (BGR, PID) are implemented, then reliability against radiation effects is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory array into multiple banks and implements EDAC encoding that processes data in segments. This segmentation allows radiation hardening to be applied to smaller, manageable units rather than the entire memory system, reducing overall device complexity while maintaining reliability through distributed error protection
Solution Approach 2:
The patent combines multiple protection mechanisms (BGR structures, PID structures, and EDAC encoding) into a composite radiation hardening approach. This composite strategy integrates process-level hardening with circuit-level hardening, achieving enhanced reliability without requiring any single technique to provide complete protection, thus managing device complexity
2Reliability
If EDAC encoding is applied to all data bits, then error-free operation is improved, but processing time increases
Solution Approach 1:
The patent implements EDAC encoding selectively rather than uniformly across all data bits. The system applies error detection and correction to critical data fields while using simpler or no protection for less critical data, reducing the overall processing overhead and time penalty while maintaining error-free operation for essential functions
Solution Approach 2:
The patent performs EDAC encoding during the write operation to memory, preparing the error-protected data in advance before it is stored. This preliminary encoding ensures that when data is retrieved, the error protection is already in place, minimizing the time penalty during critical read operations and improving overall processing efficiency
Data Source
AI summary
An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.