3D Stacked Memory Via Testing With Dynamic Chip IDs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional integrated circuits with through-chip vias face challenges in identifying faulty connections during testing, as existing methods lack efficient mechanisms to differentiate and test multiple stacked semiconductor chips simultaneously.
Innovation Solution
A semiconductor memory system that sets unique chip IDs for each chip using a chip code and performs a through-chip via test by changing these IDs during a test mode, allowing for the identification of faulty connections by activating a current source through specific vias, facilitated by a processor providing external codes and a substrate providing communication paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are stacked to form a 3D integrated circuit, then the functionality and integration density are improved, but the difficulty of detecting and measuring faulty through-chip vias increases
Solution Approach 1:
The patent divides the testing process into segments by assigning unique chip IDs to each stacked chip. This allows the test system to individually address and test each chip's through-chip vias separately, rather than treating the entire stack as a single unit. The segmentation enables systematic fault isolation and identification in multi-chip 3D integrated circuits.
Solution Approach 2:
The patent introduces chip IDs as an intermediary mechanism between the test system and the stacked chips. These IDs act as identifiers that mediate the communication and testing process, allowing the test system to selectively activate and test specific chips within the stack. This intermediary enables precise control and measurement in complex multi-chip configurations.
2Measurement precision
If chip IDs are changed during test mode period, then the measurement precision of through-chip via testing is improved, but the complexity of the testing system increases
Solution Approach 1:
The patent implements dynamic chip ID assignment where chip IDs are changed during the test mode period. This dynamic reconfiguration allows the testing system to adaptively test different chips in the stack by modifying their identifiers on-the-fly. The dynamic nature enables flexible and precise testing without requiring permanent physical modifications to each chip.
Solution Approach 2:
The patent changes the chip ID parameter during testing to differentiate between multiple stacked chips. By modifying this identification parameter dynamically, the system can precisely target and measure specific chips and their through-chip vias. This parameter change approach provides measurement precision while avoiding the need for complex physical differentiation mechanisms.
Data Source
AI summary
A semiconductor memory may include a plurality of stacked semiconductor chips which are interconnected using through-chip vias. The semiconductor memory may set chip IDs of the respective semiconductor chips by using a chip code such that the chip IDs are different from each other, and perform a through-chip via test for the plurality of stacked semiconductor chips by changing the chip IDs of the respective semiconductor chips during a test mode period.