Per-row Error Scrub Registers for Memory Data Fidelity
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Solution Overview
Problem
Current semiconductor memory devices face challenges in ensuring high fidelity of information read out due to errors in memory cells, where error correction circuits can only correct errors during read operations but not rectify the errors stored in the memory array, and there is a need for more granular error detection and correction data.
Innovation Solution
Implementing per-row error check and scrub (ECS) information registers to collect and store detailed error data for each row, enabling the option to enable or disable this feature, and using specific memory cells to store this information, allowing for error correction and reporting of error counts and addresses of rows with the most errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction circuits are used to correct errors during read operations, then information fidelity is improved, but errors stored in the memory array cannot be rectified and granular error detection data is insufficient
Solution Approach 1:
The patent segments error detection data by creating separate per-row error counters for each row in the memory array. Instead of providing only aggregate error information, the system divides error tracking into individual row segments, allowing granular identification of which specific rows contain errors and how many errors each row has accumulated.
Solution Approach 2:
The patent implements feedback mechanisms where per-row error counter values are continuously monitored and fed back to the control logic. When error counters reach threshold values, this feedback triggers automatic corrective actions such as activating error correction circuits for specific rows or initiating scrub operations to clear errors from problematic rows.
2Measurement precision
If per-row error check and scrub information registers are implemented to collect detailed error data, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the per-row error counter functionality directly into existing memory structure resources. Error counter data is stored in dedicated bits within the memory array itself or in closely integrated register structures that share control logic with the memory operations, rather than adding completely separate monitoring hardware.
Solution Approach 2:
The per-row error registers serve multiple functions: they act as error counters, address identifiers for problematic rows, and triggers for corrective actions. The same register structure supports both error detection during normal operations and initiation of scrub operations, reducing the need for separate dedicated components.
3Reliability
If error correction circuits scan every memory cell periodically to repair errors, then reliability is improved, but productivity decreases due to time consumption
Solution Approach 1:
The patent implements preliminary error detection by continuously monitoring per-row error counters during normal memory operations. Instead of waiting for periodic scans to detect errors, the system proactively identifies rows with errors as they occur and can immediately activate correction mechanisms or mark those rows for scrub operations, reducing the need for comprehensive periodic scanning.
Solution Approach 2:
The patent applies partial scanning by focusing error correction and scrub operations only on specific rows that have been identified as containing errors through the per-row counters. Instead of scanning and correcting every memory cell periodically, the system performs targeted corrections only where needed, significantly reducing the time and resources required for error correction while maintaining reliability.
Data Source
AI summary
Apparatuses, systems, and methods for per row error correct and scrub (pRECS) registers. A mode register may include a pRECS enable register, to enable a pRECS mode. When the prECS mode is enabled, pRECS information associated with each row may be collected which reflects a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row. A pRECS address register may specify a location in the memory array to store the pRECS information.