Memory Defect Map for System Reliability Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As computing systems evolve, the presence of defective memory cells can lead to system failures and increased lifecycle costs due to the growing significance of memory in overall system costs and potential data loss, despite existing methods for managing defective memory locations.
Innovation Solution
A method for creating and updating a memory defect map during both manufacturing and operation, which optimizes system performance by identifying and remapping defective memory locations, allowing the use of memory components with known defects without compromising system integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory components are tested extensively to ensure reliability, then system reliability improves, but testing time and costs increase
Solution Approach 1:
The patent applies preliminary action by creating a defect map during manufacturing testing that identifies all defective memory locations before the memory component is deployed. This preliminary identification allows the system to know in advance which locations are defective, eliminating the need for repeated testing of these known-bad locations and enabling proactive remapping strategies.
Solution Approach 2:
The patent uses copying by creating a digital representation (defect map) of the physical memory's defective locations. This defect map is a copied version of the memory's defect status that can be stored, transmitted, and processed without affecting the actual memory component, allowing the system to work with defect information efficiently.
2Reliability
If defective memory locations are remapped to spare locations, then system reliability improves, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary defect map that mediates between the physical memory component and the system's memory management. This defect map serves as an intermediate layer that translates physical defect locations into actionable remapping information, simplifying the overall system architecture by centralizing defect management rather than distributing complexity throughout the memory subsystem.
Solution Approach 2:
The remapping strategy is determined in advance based on the defect map created during manufacturing. By pre-calculating which spare locations should cover which defective locations, the system eliminates the need for complex real-time remapping decisions during operation, reducing operational complexity.
3Ease of manufacture
If memory components with defects are used, then system costs decrease, but system reliability worsens
Solution Approach 1:
The patent converts the harm of defective memory locations into a benefit by systematically identifying and mapping these defects during manufacturing. Instead of discarding memory components with defects (which would increase costs), the defect map enables the system to utilize these components effectively through remapping, transforming potential failures into acceptable operational characteristics.
Solution Approach 2:
The memory component essentially serves itself by including the defect map within the component or associated with it. The defect information is self-contained within the memory component, allowing the system to automatically identify and compensate for defects without requiring external intervention or complex external testing infrastructure.
4Measurement precision
If a comprehensive defect map is maintained, then memory management precision improves, but memory access time increases
Solution Approach 1:
The defect map is pre-populated during manufacturing with all known defective locations identified through comprehensive testing. This preliminary action ensures that the defect map is complete and accurate before the memory component enters service, eliminating the need for runtime defect detection and allowing the system to make precise remapping decisions instantly.
Solution Approach 2:
The patent extracts defect information from the physical memory testing process and separates it into a distinct defect map data structure. This extraction allows the defect information to be processed independently from normal memory operations, enabling precise memory management without requiring the entire defect map to be checked during every memory access.
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A method for storing a memory defect map is disclosed whereby a memory component is tested for defects at the time of manufacture and any memory defects detected are stored in a memory defect map and used to optimize the system performance. The memory defect map is updated and the system's remapping resources optimized as new memory defects are detected during operation.