Parallel Memory Test Circuit with Module Selection and Comparator
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Solution Overview
Problem
Conventional parallel testing of multiple memory modules is limited by the size of the input data memory and requires unnecessary components during the test phase, which constraints the amount of test data that can be verified and increases complexity.
Innovation Solution
A semiconductor device with a module selection circuit that can individually select memory modules in regular operation and collectively select multiple modules for parallel testing, using a comparator circuit to verify output data consistency across modules, and an optional cyclical redundancy check, allowing for efficient parallel testing of memory modules of varying sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional parallel testing is used with input data memory, then testing speed is improved, but device complexity increases and test data size is constrained
Solution Approach 1:
The patent extracts and removes the input data memory component from the parallel testing architecture. Instead of storing test data in memory, the system directly compares output data from multiple memory modules in real-time, eliminating the need for separate storage infrastructure and reducing overall device complexity while maintaining parallel testing capabilities
Solution Approach 2:
The comparator circuit is designed to serve multiple functions: it simultaneously compares output data from multiple memory modules, validates data integrity, and identifies faulty modules. This multi-functional approach replaces what would otherwise require separate verification components, reducing device complexity while enhancing testing productivity
2Productivity
If input data memory is used for parallel testing, then testing capacity is improved, but the amount of verifiable test data is constrained
Solution Approach 1:
The patent transitions from a time-based testing approach (where data is stored and processed sequentially through memory) to a spatial comparison approach (where output data from multiple modules are compared simultaneously). This dimensional shift in the testing architecture allows for verification of larger test data sets by utilizing parallel comparison paths rather than sequential memory access
3Productivity
If conventional parallel testing architecture is used, then testing efficiency is improved, but unnecessary components are required during test phase
Solution Approach 1:
The patent removes unnecessary components such as input data memory and separate verification units from the testing architecture. The streamlined design uses only the essential comparator circuit that can operate in parallel testing mode without requiring additional dedicated hardware, thereby maintaining testing efficiency while reducing device complexity
Solution Approach 2:
The comparator circuit is designed to be multi-functional, serving both as a data comparison unit and a verification unit. This eliminates the need for separate verification components that would otherwise be required during the test phase, reducing device complexity while preserving testing efficiency
Data Source
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AI summary
The invention relates to a semiconductor device (DV1) comprising N memory modules (MEM0 _MEMN-1), N being greater than or equal to three, each module comprising an array of memory cells arranged in rows and columns, a write circuit (WCT) coupled to each module and configured to write data (ID) in the memory cells, a read circuit (RCT) coupled to each module and configured to supply output data (OD0 _ODN-1) from the memory cells, a module selection circuit (MDEC) configured to individually select one memory module (MEM0 _MEMN-1) in a regular operation mode, and to collectively select two or more of the modules in a parallel mode, and a comparator circuit (CMP) coupled to the N modules and configured to compare, in the parallel mode, the output data supplied by the N modules.