Memory Device Multi-Bit Error Self-Repair via Segmented Reading Cycles
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Solution Overview
Problem
Current memory devices can only detect and repair single-bit errors using error correction codes (ECC), failing to handle multiple-bit errors, which leads to erroneous read results.
Innovation Solution
A memory device and control method that includes a memory cell array, repairing memory cells, and a readout and detection circuit, enabling multiple reading cycles to identify and correct multiple erroneous bits by writing correct data to corresponding repairing memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ECC algorithm is used for error detection and repair, then single-bit errors can be detected and repaired, but multiple-bit errors cannot be handled
Solution Approach 1:
The patent segments the error handling process into multiple reading cycles. The first reading cycle detects initial errors, and subsequent reading cycles continue detection until no errors remain. This segmentation allows the system to handle multiple-bit errors by breaking down the correction process into manageable steps, with each cycle addressing remaining errors until the data is fully corrected.
2Reliability
If multiple reading cycles are implemented to detect multiple-bit errors, then error detection capability is improved, but reading time increases
Solution Approach 1:
The patent implements periodic reading cycles where the memory device performs multiple sequential reads. After the first reading cycle detects errors, subsequent reading cycles are triggered to verify correction and detect any remaining errors. This periodic action ensures reliable multi-bit error detection while systematically reducing the time penalty through structured, repeated verification.
3Ease of repair
If repairing memory cells are used to store correct data, then self-repair capability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the memory device to automatically detect errors, determine the need for repair, and trigger writing cycles to correcting memory cells without external intervention. The controller autonomously manages the entire repair process, including detecting erroneous bits in readout data and initiating correction writes, thereby improving ease of repair while keeping the control logic integrated within the existing device architecture.
Data Source
AI summary
A memory device and a control method for the memory device are provided. When it is determined that a bit read from a memory cell in a memory cell array is an erroneous bit, the memory device triggers a second reading cycle. During the second reading cycle, if the bit read from the same memory cell is still an erroneous bit, the memory cell is deemed to be a real defective memory cell. At this time, a repairing memory cell is selected from a repairing memory cell array to replace the real defective memory cell. The selected repairing memory cell and the real defective memory cell are coupled to the same word line.