Adaptive Non-Volatile Memory Mode Switching for Timeout Resolution
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Solution Overview
Problem
Non-volatile memory systems face challenges in optimizing programming performance, particularly in large block structures, where increased storage density and reliability are compromised due to trade-offs between speed and power consumption, leading to potential timeouts during operations like garbage collection and data relocation.
Innovation Solution
The memory system adapts its performance by switching between normal and high-performance modes based on detected system situations, such as high latency or reliability issues, by altering clock rates, programming pulse characteristics, or error correction mechanisms, to minimize timeouts while maintaining reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory system uses normal programming mode to maintain reliability and reduce power consumption, then reliability and power efficiency are improved, but programming speed deteriorates leading to potential timeouts during operations
Solution Approach 1:
The memory system dynamically switches between normal programming mode and high-performance programming mode based on detected system situations. When a situation requiring faster completion is detected (such as during garbage collection or data relocation operations), the system transitions to high-performance mode to complete the operation before timeouts occur, then returns to normal mode afterward. This dynamic adaptation resolves the contradiction by allowing the system to optimize for speed when necessary and for reliability when conditions permit.
2Productivity
If the memory system increases programming speed to avoid timeouts, then productivity is improved, but power consumption increases
Solution Approach 1:
The system employs dynamic mode switching that activates high-performance programming mode only when system situations indicate a risk of timeout (such as during garbage collection or data relocation). This selective activation ensures that increased power consumption occurs only when necessary to maintain productivity, rather than operating at high power consumption continuously. After the critical operation completes, the system returns to normal mode to reduce power consumption during routine operations.
3Productivity
If the memory system uses high-performance mode continuously to ensure fast operation completion, then productivity is improved, but reliability and power consumption worsen
Solution Approach 1:
The memory system uses situation detection mechanisms to determine when high-performance mode is actually needed, rather than operating in high-performance mode continuously. The system switches to high-performance mode only when detecting specific situations (such as ongoing garbage collection or data relocation operations) where timeout risks exist. For all other operations, the system operates in normal mode which maintains better reliability and lower power consumption, thus avoiding the drawbacks of continuous high-performance mode operation.
4Loss of time
If the memory system switches to high-performance mode during critical operations, then operation completion time is reduced avoiding timeouts, but device complexity increases
Solution Approach 1:
The system implements a situation-aware dynamic mode switching mechanism that monitors system operations and automatically transitions between normal and high-performance modes based on detected conditions. This approach reduces operation latency during critical operations like garbage collection and data relocation by activating high-performance mode only when necessary, rather than using static mode selection. The situation detection and automatic switching infrastructure adds some complexity but enables timely responses to critical operations while maintaining simplicity in normal operation scenarios.
Data Source
AI summary
The present invention presents a non-volatile memory system that adapts its performance to one or more system related situation. If a situation occurs where the memory will require more than the allotted time for completing an operation, the memory can switch from its normal operating mode to a high performance mode in order to complete the operation quickly enough. Conversely, if a situation arises where reliability could be an issue (such as partial page programming), the controller could switch to a high reliability mode. In either case, once the trigging system situation has returned to normal, the memory reverts to the normal operation. The detection of such situations can be used both for programming and data relocation operations. An exemplary embodiment is based on firmware programmable performance.