Adaptive Digital PLL Bandwidth Control for Low Jitter Tracking
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Solution Overview
Problem
Digital phase locked loop (DPLL) circuits face issues with quantization noise and jitter performance due to the introduction of noise sources in digital phase-frequency detectors and digitally controlled oscillators, degrading phase noise and jitter.
Innovation Solution
A digital PLL with a dynamically controllable filter that adjusts bandwidth in response to real-time phase error, using adjustable filter coefficients to maintain low jitter while ensuring sufficient tracking responsiveness, by dynamically altering the loop bandwidth based on phase error levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed bandwidth filter is used in DPLL, then the circuit structure is simple, but jitter performance degrades due to quantization noise
Solution Approach 1:
The patent implements a dynamic bandwidth control mechanism where the filter bandwidth is adjusted in real-time based on the detected jitter level. When jitter exceeds a threshold, the bandwidth is reduced to attenuate quantization noise; when jitter is acceptable, bandwidth is increased to improve tracking responsiveness. This dynamic adaptation resolves the contradiction by making the filter structure flexible rather than fixed.
Solution Approach 2:
The patent changes the filter parameters (bandwidth) dynamically based on operating conditions. By monitoring phase error and adjusting the loop filter coefficients accordingly, the system optimizes the trade-off between noise attenuation and tracking performance, thereby improving jitter performance without requiring a permanently complex filter structure.
2Speed
If loop bandwidth is increased to improve tracking responsiveness, then phase error correction is faster, but jitter increases due to noise amplification
Solution Approach 1:
The system dynamically adjusts loop bandwidth based on real-time phase error conditions. During transient states when phase error is large, the bandwidth is increased to accelerate convergence. Once locked and phase error is small, the bandwidth is reduced to minimize jitter. This time-varying bandwidth control resolves the contradiction between tracking speed and jitter performance.
Solution Approach 2:
The patent employs periodic monitoring of phase error and jitter levels, with bandwidth adjustments made at specific intervals or triggering events. This periodic control approach allows the system to maintain high tracking responsiveness when needed while periodically reducing bandwidth to control jitter, achieving both objectives through rhythmic parameter adjustment.
3Reliability
If loop bandwidth is reduced to decrease jitter, then noise attenuation is improved, but tracking responsiveness decreases
Solution Approach 1:
The patent makes the loop bandwidth dynamic rather than fixed at a low value. The bandwidth control unit monitors system state and increases bandwidth temporarily when rapid tracking is required, then reduces it for noise attenuation during steady-state operation. This dynamic behavior resolves the contradiction by providing high responsiveness only when necessary while maintaining low jitter during normal operation.
Data Source
AI summary
In some embodiments, a digital PLL is disclosed with a dynamically controllable filter for changing the effective DPLL bandwidth in response to one or more real-time performance parameters such as phase error.