Adaptive Precharge Scheduler for DRAM Refresh Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The refresh process in DRAM memory systems negatively affects performance and power usage, as it stalls data access and increases power consumption due to the periodic reading and rewriting of data across all DRAM banks.
Innovation Solution
An adaptive precharge scheduler is integrated into the memory controller to monitor traffic and intelligently insert precharges within the traffic stream, allowing the refresh scheduler to issue refresh per bank commands (REFpb) in a sequence that minimizes disruption to system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If REFab (refresh all banks) command is used to refresh DRAM banks, then all DRAM banks are refreshed, but all banks become unavailable causing system blackout
Solution Approach 1:
The patent divides the DRAM bank refresh operation into separate per-bank REFpb commands instead of a single all-bank REFab command. This segmentation allows individual banks to be refreshed independently while others remain available for data access, eliminating the system blackout problem while ensuring complete refresh of all banks.
Solution Approach 2:
The adaptive precharge scheduler proactively issues PRE commands to close rows in DRAM banks before refresh operations are needed. This preliminary action prepares banks for efficient per-bank refresh operations, enabling the refresh scheduler to issue REFpb commands without requiring all banks to be in idle state, thus avoiding system unavailability.
2Productivity
If REFpb (refresh per bank) commands are used to refresh individual DRAM banks, then system traffic continues on other banks, but refresh scheduling becomes complex
Solution Approach 1:
The adaptive precharge scheduler continuously monitors DRAM traffic patterns and bank usage status, using this feedback to dynamically determine which banks need precharging and when. This feedback mechanism enables intelligent, traffic-aware refresh scheduling that automatically adapts to changing system conditions, managing complexity through observation and response rather than rigid predetermined sequences.
Solution Approach 2:
The memory controller autonomously manages the refresh scheduling process by automatically detecting traffic conditions, selecting appropriate banks for precharge, and coordinating REFpb commands without external intervention. The system self-regulates the refresh process based on real-time operational state, reducing the need for complex external control while maintaining high throughput.
3Productivity
If precharge commands are inserted frequently to enable per-bank refresh, then refresh operations can proceed without blocking traffic, but DRAM rows may be closed unnecessarily
Solution Approach 1:
The adaptive precharge scheduler dynamically adjusts precharge scheduling parameters based on real-time DRAM traffic analysis. By monitoring actual usage patterns and bank occupancy, the system changes precharge timing and frequency parameters adaptively, issuing precharges only when necessary to enable refresh operations without unnecessarily closing already-open rows, thus avoiding wasted energy consumption.
Data Source
AI summary
This specification describes memory controllers with adaptive precharge scheduling. In one aspect, a memory controller includes a refresh scheduler configured to send refresh commands to dynamic random-access memory (DRAM) banks of a DRAM memory system that includes DRAM banks arranged in a set of DRAM bank groups each comprising one or more DRAM banks. The memory controller includes an adaptive precharge scheduler configured to determine a priority score for each DRAM bank group based on a set of parameters, select, based on the priority score for each DRAM bank group, a particular DRAM bank group to close so that each DRAM bank in the DRAM bank group can be refreshed by the refresh scheduler, and send the precharge command to at least one DRAM bank of the particular DRAM group.