Adaptive Reference Voltage Refresh via Parasitic Leakage
Solution Overview
Problem
Existing methods for controlling the refresh rate of a reference voltage on a sampling capacitor in integrated electronic devices result in high power consumption and chip area usage due to the need for additional reference voltage generators and fixed periodic refresh cycles, which do not account for varying leakage currents.
Innovation Solution
The implementation of a circuitry system using two capacitors and leakage current sources with a controlled ratio, eliminating the need for an additional reference voltage generator and allowing for adaptive refresh based on actual leakage current conditions, thereby reducing power consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a comparator with additional reference voltage generator and biasing circuitry is used to control refresh, then the reference voltage can be maintained within a certain range, but the power consumption and chip area increase significantly
Solution Approach 1:
The invention extracts and utilizes the inherent parasitic leakage currents that naturally exist in the sampling capacitor and associated circuitry. By measuring these leakage currents directly, the patent eliminates the need for additional reference voltage generators and complex biasing circuitry, thereby reducing power consumption while maintaining reference voltage integrity through adaptive refresh control
Solution Approach 2:
The system uses its own internal parasitic leakage currents to generate the refresh control signal. The sampling capacitor's natural leakage behavior serves as the basis for determining when refresh is needed, eliminating the need for external reference voltage sources and reducing overall power consumption while maintaining reliability
2Reliability
If a fixed periodic refresh cycle is used for worst case leakage, then the reference voltage is always refreshed, but the power consumption and refresh rate are unnecessarily high
Solution Approach 1:
The invention transitions from a static fixed-period refresh approach to a dynamic refresh mechanism. The refresh period is continuously adjusted based on the measured parasitic leakage current, allowing the system to operate efficiently under low leakage conditions while ensuring adequate refresh frequency when leakage increases, thereby optimizing power consumption without compromising reliability
Solution Approach 2:
The system implements a feedback mechanism where the parasitic leakage current is measured and used to control the refresh timing. This closed-loop approach ensures that refresh operations are performed only when necessary, matching the actual leakage behavior rather than using a conservative fixed schedule, thus reducing unnecessary power consumption while maintaining reference voltage integrity
3Measurement precision
If additional reference voltage generator and biasing circuitry are added, then the reference voltage comparison can be performed, but the chip area increases
Solution Approach 1:
The invention extracts and utilizes the inherent parasitic leakage currents that naturally exist in the sampling capacitor and associated circuitry. By measuring these leakage currents directly, the patent eliminates the need for additional reference voltage generators and complex biasing circuitry, thereby reducing power consumption while maintaining reference voltage integrity through adaptive refresh control
Solution Approach 2:
The sampling capacitor and its associated leakage paths serve multiple functions: they store the reference voltage, generate the leakage current signal for measurement, and provide the basis for refresh control. This multi-functionality eliminates the need for dedicated reference voltage generators and biasing circuitry, reducing chip area while maintaining voltage comparison capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves significant power savings and flexible refresh timing that adapts to temperature changes, reducing unnecessary power consumption and chip area requirements.
Implementation Method 1
The voltage on the sampling capacitor decreases over time primarily by parasitic leakage currents
Data Source
Figure 1~3
Figure 4~5
AI summary
The present invention relates to controlling the refresh rate of the reference voltage on a sampling capacitor (CsamP). A comparator (COMP) compares the voltage on a first capacitor (C1) with the voltage on a second capacitor (C2). These capacitors have the capacitance of the sampling capacitor (CsamP). Upon each refresh the first capacitor (C1) samples a first voltage (Va) and the second capacitor samples a lower second voltage (Vb). The first capacitor (C1) is discharged at a first current Ia via a first leakage current source (D1). The second capacitor (C2) is discharged at a second current Ib via a second leakage current source (D2). The comparator (COMP) triggers a refresh when the voltages equal. The first current Ia is preferably an integer N times the second current Ib.