Electric Analogue Stores TRIZ Cases
- Charge Pump Efficiency Tracking via Dynamic Parameter Adjustment
A charge pump uses a maximum efficiency point tracking system to measure and compare successive output voltage values for self-adaptation.
- Integrated Circuit Noise Cancellation Using Auxiliary Capacitor
Auxiliary capacitor isolates thermal noise from sampled signals, eliminating residual interference in switched capacitor circuits.
- Flash Cell Voltage Reference Generator for Compact IC Design
A voltage reference generator uses flash cells with variable threshold voltages to trim reference signals in closed loop circuits.
- Analog CAM Using Three-Terminal Devices for Area and Power Reduction
Three-terminal memory devices enable analog content addressable memory cells to store multilevel voltages, reducing device area and power consumption.
- Sample and Hold Circuit Using Dual Capacitor Segmentation for High Voltage Sampling
A sample and hold circuit segments voltage sampling across two capacitors to handle signals exceeding component tolerance.
- Ferroelectric Select Transistor for Linear Conductance Tuning
A ferroelectric select transistor modulates programming current to tune resistive memory conductance.
- Oscillator Array Associative Memory for Grayscale Pattern Matching
Voltage-controlled oscillators shift frequencies to match grayscale patterns, eliminating phase detectors and reducing hardware complexity.
- Sample and Hold Leakage Compensation via Segmented Capacitors
Segmented capacitors model leakage current to subtract accumulated charge, maintaining measurement precision without increasing circuit area.
- Error Compensation Circuit for Analog Capacitor Memory
An error compensation circuit refreshes analog memory capacitors using dedicated transistors and switches to maintain stored voltage levels.
- PCM Drift Compensation via Sequential Pulse Control
Control circuitry sends identical pulses to phase change memory resistors sequentially to adjust reference resistance values.
- Sense Amplifier Circuit with Miller Effect Feedback
A sense amplifier circuit uses an integrating capacitor in a feedback path to supply current and integrate charge during memory cell read operations.
- Offset Cancellation Latch Sense Amplifier for Non-Volatile Memory
Parallel cross-coupled latches cancel transistor mismatch during zeroing, enabling faster sensing in non-volatile memory.
- Memory Reference Cells Adjust ADC Window for Multi-Level Cell Read Speed
Reference cells define conversion window limits to retrieve multi-bit patterns, reducing operation times caused by binary read constraints.
- Analog Memory Device With Multi-Sensitivity Cells For Neural Weights
Multi-deck memory cells with varying programming sensitivities extend the analog storage range for neuro-biological architectures.
- Phase Change Memory Interface Circuitry for Multi-Level State Detection
External interface circuitry conditions signals to resolve resistance state distinction errors during multi-level programming operations.
- Sense Amplifier Isolation for Non-Volatile Memory Read Speed
Isolating the sense amplifier from bit line load during evaluation reduces read access time and power consumption.
- Discharging Circuit Stabilizes Semiconductor Memory Read Current
A discharging circuit clears residual electric charges from interconnections between memory operations.
- Dynamic Verification Relaxation for Non-Volatile Memory Programming
A dynamic verification method adjusts programming thresholds during memory cell operations to balance speed and reliability.