Electric Analogue Stores TRIZ Cases

A charge pump uses a maximum efficiency point tracking system to measure and compare successive output voltage values for self-adaptation.

Auxiliary capacitor isolates thermal noise from sampled signals, eliminating residual interference in switched capacitor circuits.

A voltage reference generator uses flash cells with variable threshold voltages to trim reference signals in closed loop circuits.

Three-terminal memory devices enable analog content addressable memory cells to store multilevel voltages, reducing device area and power consumption.

A sample and hold circuit segments voltage sampling across two capacitors to handle signals exceeding component tolerance.

A ferroelectric select transistor modulates programming current to tune resistive memory conductance.

Voltage-controlled oscillators shift frequencies to match grayscale patterns, eliminating phase detectors and reducing hardware complexity.

Segmented capacitors model leakage current to subtract accumulated charge, maintaining measurement precision without increasing circuit area.

An error compensation circuit refreshes analog memory capacitors using dedicated transistors and switches to maintain stored voltage levels.

Control circuitry sends identical pulses to phase change memory resistors sequentially to adjust reference resistance values.

A sense amplifier circuit uses an integrating capacitor in a feedback path to supply current and integrate charge during memory cell read operations.

Parallel cross-coupled latches cancel transistor mismatch during zeroing, enabling faster sensing in non-volatile memory.

Reference cells define conversion window limits to retrieve multi-bit patterns, reducing operation times caused by binary read constraints.

Multi-deck memory cells with varying programming sensitivities extend the analog storage range for neuro-biological architectures.

External interface circuitry conditions signals to resolve resistance state distinction errors during multi-level programming operations.

Isolating the sense amplifier from bit line load during evaluation reduces read access time and power consumption.

A discharging circuit clears residual electric charges from interconnections between memory operations.

A dynamic verification method adjusts programming thresholds during memory cell operations to balance speed and reliability.

Hierarchical bit lines with multiplexers lower power consumption and minimize disturbances in unselected memory cells.

A memory unit splits multi-bit input signals into sub-groups and stacks converted voltages to perform parallel computing operations.

Charge domain digital circuits leverage FinFET technology to manipulate electrical charge packets for logic operations.

Status memory cells store word line programming states to configure readout operations for analog memory arrays.

A magnetic field rotates the free layer magnetization orientation in spin-transfer torque memory to enable self-reference read operations.

Parallel saturation-mode transistors redirect harmonic currents away from sampling capacitors to improve SFDR.

Controlling the MOS transistor bulk voltage equalizes potential differences, which suppresses leakage currents in sample and hold stages.

Segmented sensing amplifier groups reduce power consumption and noise while maintaining rapid initial data reading speeds in memory arrays.

SRAM cells perform analog current summation to generate accumulated signals, bypassing the von Neumann bottleneck.

Passive switch network isolates latch inputs to reduce area and power consumption.

Multiple latches sample voltages at different timings to correct read errors, reducing retry time and improving measurement precision.

Capacitors in the second stage store mismatch voltages to cancel FET errors, improving read accuracy at low voltage.

A comparator circuit triggers sampling capacitor refresh using controlled parasitic leakage currents.

High-pass filtering extracts frequency components from memory signals, converting them to DC values to resolve speed versus reliability trade-offs.

A strobe signal controlling circuit synchronizes write pulse signals with clock signals using an initial write controller.

A tracking circuit monitors threshold voltage to generate sensing parameters for memory state detection.

Adjustable shielding in the intermediate layer achieves high capacitive swing ratio without varying plate spacing, preserving lateral scalability.

A sense amplifier uses a sampling capacitor to store reference voltage and control transistor conductivity for accurate memory read operations.

Memristor memory maps data to continuous memductance values, increasing storage density and reducing decoder size.

A dual sampling and holding circuit architecture alternates analog data voltage supply to liquid crystal display panels while compensating offset voltages.

A switched memristor array provides programmable resistance values to tune analog circuit characteristics through discrete selection.

A sample-and-hold circuit uses a second transistor and specific gate voltage to reduce charge injection noise.

A sample and hold circuit stabilizes output current using a control MOSFET with negative temperature coefficient paired with cascaded cells having positive thermal characteristics.

A sample and hold circuit captures voltage at a transistor switch midpoint to provide stable current data for the sensing system.

A magnetic tunnel junction stack uses voltage-controlled magnetic anisotropy to alter spin orientation and resistance levels.

Amplifier measures offset voltage to minimize sampling switch leakage, extending hold time and reducing power consumption.

A dynamic shift register circuit samples incoming signals and generates non-overlapped output signals using integrated logic.

Segmented signal lines with universal buffers reduce propagation delay and power consumption in integrated circuits.

A converter circuit charges a storage capacitor only during positive AC half-cycles to supply regulated DC power.

Periodic recreating voltages restore conductive filaments in RRAM cells, recovering the resistance window degraded by repeated set-reset cycles.

Dynamic reference signals track performance degradation to maintain sense window stability and reduce power consumption during memory access operations.