Sense Amplifier Circuit with Miller Effect Feedback

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Solution Overview

Problem

The increasing number of reference threshold voltages in semiconductor memory devices, such as MLC, TLC, and QLC, leads to longer read times and susceptibility to operation variations in determining whether memory cells are on or off, affecting the reliability of data retrieval.

Innovation Solution

A sense amplifier circuit with an integrating capacitor and a discrete time amplifier configuration, which includes a feedback path and a miller effect to enhance voltage gain and reduce operation variation, allowing for reliable determination of memory cell states across varying threshold voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of reference threshold voltages is increased to support multi-level memory cells (MLC, TLC, QLC), then the storage capacity is improved, but the read time increases and the circuit becomes more susceptible to operation variations

Engineering Contradiction:
Improvestorage capacityVSAvoidread time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The sense amplifier circuit performs sequential comparisons against multiple reference threshold voltages in a periodic manner, with each comparison cycle using a different reference voltage. This structured periodic approach allows systematic determination of multi-level data while managing the increased complexity through organized repetition of the comparison process

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

Reference threshold voltages are pre-established and stored in reference voltage generation circuits before the actual read operation begins. This preliminary preparation of reference voltages allows the sense amplifier to immediately perform comparisons without delay, reducing the overall read time despite multiple comparison steps being required

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If the read time at one reference threshold voltage is shortened, then the overall read time is reduced, but the circuit becomes more susceptible to operation variations in determining whether the memory cell is on or off

Engineering Contradiction:
Improveread timeVSAvoiddetermination reliability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The sense amplifier circuit incorporates feedback mechanisms where the output of each comparison stage feeds into the next stage. This feedback approach allows the circuit to maintain stability and reliability by continuously monitoring and adjusting based on previous comparison results, even when operating at reduced time margins

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The circuit design includes built-in time margins and voltage margins that act as cushions against operation variations. By designing with these protective margins in advance, the circuit can tolerate shorter read times without sacrificing reliability, as the margins provide a buffer against timing skew and voltage fluctuations

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Measurement precision

If the number of reference threshold voltages is increased, then the data value determination capability is improved, but the device complexity increases

Engineering Contradiction:
Improvedata value determination capabilityVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The sense amplifier circuit is divided into multiple independent comparison stages, with each stage handling one reference threshold voltage comparison. This segmentation allows the complex multi-level determination task to be broken down into simpler, manageable sub-tasks, reducing overall circuit complexity while maintaining high measurement precision

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sense amplifier circuit is designed with universal components that can handle multiple reference threshold voltage comparisons using the same basic circuit architecture. This multi-functionality approach allows a single circuit design to support MLC, TLC, and QLC configurations without requiring entirely separate circuits for each, thereby managing complexity while maintaining determination capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed sense amplifier circuit significantly increases the gain and provides a larger voltage margin between on and off states, reducing the influence of operation variations and improving the reliability of data retrieval, especially in multi-level memory cells.

Implementation Method 1

a first capacitor configured to be connected in a feedback path of the amplification transistor and to a bit line of a memory cell via the sense node, the first capacitor configured to supply a current to the memory cell and integrate the current when the memory cell is read

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

A sense amplifier circuit with an integrating capacitor and a discrete time amplifier configuration, which includes a feedback path and a miller effect to enhance voltage gain

Methodology Applied
Scientific EffectMiller effect:

Data Source

PatentUS11183230B2Sense amplifier circuit and semiconductor memory device
Publication Date: 2021.11.23 KIOXIA CORP
  • US11183230B2 patent drawing
  • US11183230B2 patent drawing
  • US11183230B2 patent drawing

AI summary

According to one embodiment, a sense amplifier circuit includes an amplifier having an input terminal connected to a sense node, and a first capacitor configured to be connected in a feedback path of the amplification transistor and to a bit line of a memory cell via the sense node, the first capacitor configured to supply a current to the memory cell and integrate the current when the memory cell is read.