Memory Reference Cells Adjust ADC Window for Multi-Level Cell Read Speed
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Solution Overview
Problem
Traditional solid-state memory devices face inefficiencies in programming and reading operations due to their binary nature, which becomes increasingly troublesome as more bits are stored on each multi-level cell (MLC), leading to longer operation times and lower storage capacities compared to mechanical hard disk drives (HDDs).
Innovation Solution
The memory devices utilize threshold voltage ranges to represent multiple data values, allowing for single read and write operations that return complete bit patterns, rather than discrete bits, and employ reference cells to adjust the analog-to-digital conversion window, enabling more efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If binary read/write operations are used in traditional MLC devices, then data storage is simplified, but operation times increase and storage capacity decreases when storing multiple bits per cell
Solution Approach 1:
The patent segments the threshold voltage range into multiple distinct ranges, each representing a different data value. Instead of binary operations, the system performs analog voltage measurements and compares the measured threshold voltage against multiple reference voltages to directly determine multi-bit data values in a single operation, thereby reducing operation times while handling increased storage capacity
Solution Approach 2:
The patent changes the parameter representation from binary states to continuous threshold voltage ranges. By measuring the actual threshold voltage value and comparing it against multiple reference voltages, the system can retrieve multiple bits of data in a single read operation, improving productivity without proportionally increasing operational complexity
2Quantity of substance
If more bits are stored on each multi-level cell, then storage capacity increases, but operation times become longer due to binary operation limitations
Solution Approach 1:
The patent performs preliminary actions by pre-establishing multiple reference voltage levels corresponding to different threshold voltage ranges during device initialization. These reference voltages are stored in reference cells and used during read operations to enable direct comparison and immediate determination of multi-bit data values, eliminating the need for sequential binary operations and significantly reducing operation time
Solution Approach 2:
The patent replaces the mechanical sequential binary read/write operations with an analog measurement and comparison system. By measuring the threshold voltage continuously and comparing it against multiple reference voltages in parallel, the system can retrieve multiple bits simultaneously, reducing operation time while maintaining high storage capacity
3Productivity
If threshold voltage ranges are used to represent multiple data values, then single read operations can return complete bit patterns, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements feedback mechanisms where reference cells are programmed with precise reference voltages that correspond to the boundaries between different threshold voltage ranges. During read operations, the measured threshold voltage is compared against these reference voltages, and the comparison results provide feedback to determine the correct data value. This feedback system ensures accurate data retrieval even with variations in manufacturing precision
Solution Approach 2:
The patent uses reference cells as copies or templates that store ideal reference voltage values. These reference cells are programmed during manufacturing to represent the exact threshold voltage boundaries, and they serve as comparison standards during read operations. By copying the ideal threshold voltage ranges into reference cells, the system achieves high manufacturing precision without requiring extreme precision in the main memory cells
Data Source
AI summary
An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array.