Offset Cancellation Latch Sense Amplifier for Non-Volatile Memory
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Solution Overview
Problem
Sense amplifiers in non-volatile memory face challenges due to mismatch in the input stage of latch-type amplifiers, affecting sensitivity and minimum voltage differential sensing, which limits their performance and speed.
Innovation Solution
A sense amplifier design featuring cross-coupled latches that operate in parallel states, allowing for zeroing and sensing phases concurrently, utilizing charging and discharging phases to cancel transistor mismatches and enhance voltage comparison efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a latch-type sense amplifier is used to detect and amplify signals from memory cells, then the amplifier can provide signal amplification and regeneration, but mismatch in the input stage determines sensitivity and minimum voltage differential that can be sensed, limiting performance
Solution Approach 1:
The sense amplifier is divided into two separate cross-coupled latches: a first latch dedicated to offset cancellation and a second latch dedicated to sensing. This segmentation allows each latch to be optimized for its specific function, with the first latch eliminating transistor mismatch effects and the second latch performing high-precision sensing, thereby resolving the contradiction between measurement precision and reliability
Solution Approach 2:
The first cross-coupled latch acts as an intermediary component that preprocesses the bit line signals by canceling offset voltages caused by transistor mismatch before the signals are passed to the second latch for sensing. This intermediary offset cancellation stage improves the reliability of the overall sensing operation by removing systematic errors
2Measurement precision
If the sense amplifier performs zeroing operation before sensing, then offset cancellation can be achieved, but the time required for zeroing reduces the overall sensing speed
Solution Approach 1:
By segmenting the sense amplifier into two parallel latches with distinct functions, the offset cancellation and sensing operations can be performed simultaneously on different latch structures, eliminating the sequential time penalty and improving sensing speed while maintaining offset cancellation accuracy
Solution Approach 2:
The first cross-coupled latch performs preliminary offset cancellation action on the bit line signals before they are sensed by the second latch. This preliminary action removes systematic errors in advance, allowing the second latch to focus solely on high-speed sensing without being burdened by offset correction requirements
3Reliability
If cross-coupled latches operate sequentially with zeroing phase followed by sensing phase, then offset cancellation can be performed, but the zeroing time cannot be viewed as zero and sensing speed is limited
Solution Approach 1:
The sense amplifier is segmented into two independent cross-coupled latches that operate in parallel, allowing offset cancellation and sensing to occur simultaneously rather than sequentially. This eliminates the time loss associated with sequential operation while maintaining reliable offset cancellation through the dedicated first latch
Solution Approach 2:
The two cross-coupled latches operate continuously and simultaneously in parallel, with the first latch continuously performing offset cancellation while the second latch continuously performs sensing. This continuous parallel operation eliminates idle time and maximizes the utilization of both latches, resolving the time loss issue
Data Source
AI summary
A method provided herein is adapted to a sense amplifier having a first cross-coupled latch and a second cross-coupled latch, each of which includes a first pair of transistors and a pair of coupling capacitors coupled to respective gate terminals of the first pair of transistors. The method includes, during a first phase, charging the pair of coupling capacitors of a first pair of transistors at a first cross-coupled latch to achieve zeroing and providing a first set of input voltages to a second cross-coupled latch, and, during a second phase following the first phase, discharging the pair of coupling capacitors to cancel a mismatch between the first pair of transistors and comparing the first set of input voltages provided to the second cross-coupled latch to generate a first set of output voltages.