Ferroelectric Select Transistor for Linear Conductance Tuning

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Solution Overview

Problem

Tunable resistive memory devices in neuromorphic computing systems face challenges in achieving symmetric and linear conductance tuning, leading to errors in synaptic weight updates due to non-linear conductance evolution with pulse applications, which is crucial for efficient machine learning and inference processing.

Innovation Solution

The implementation of ferroelectric select transistors, specifically ferroelectric field-effect transistors (FeFET) devices, which modulate the polarization state in response to programming pulses to achieve linear conductance tuning of resistive memory devices using identical pulses, enhancing the linearity of conductance changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional resistive memory devices are used for synaptic weight updates, then the basic memory function is achieved, but non-linear conductance evolution with pulse applications causes errors in synaptic weight updates

Engineering Contradiction:

Improveconductance tuning linearityVSAvoidsynaptic weight update accuracy

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

A FeFET device is introduced as an intermediary between the word line and the resistive memory device. The FeFET's polarization state acts as a mediator that transforms the relationship between applied pulses and conductance changes, enabling linear conductance evolution through voltage-controlled partial polarization switching while the resistive memory device maintains its non-volatile storage function

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the electrical parameters of the memory cell by introducing a ferroelectric field-effect transistor that provides voltage-controlled modulation of the programming current. The FeFET's polarization state can be modulated by programming pulses, which in turn modulates the current flowing through the resistive memory device, achieving linear incremental conductance changes

Inventive Principle:

Principle #35Parameter changes

2Ease of operation

If identical programming pulses are applied to tune conductance, then the programming process is simplified, but non-linear conductance evolution occurs without FeFET modulation

Engineering Contradiction:

Improveprogramming pulse simplicityVSAvoidconductance tuning linearity

Core Design Contradiction:

Ease of operationVSManufacturing precision

Solution Approach 1:

The FeFET device serves as a mediator that receives simple identical programming pulses on its gate terminal and transforms them into linearly progressive conductance changes in the resistive memory device through its polarization switching characteristics

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The FeFET device introduces dynamic polarization switching behavior that responds to identical pulses by progressively changing its polarization state, which dynamically modulates the programming current to achieve linear conductance evolution in the resistive memory device

Inventive Principle:

Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the linearity of conductance tuning, reducing errors in synaptic weight updates and enabling efficient neuromorphic computing by using the dynamics of voltage-controlled partial polarization switching in FeFET devices, allowing for precise and symmetric incremental changes in conductance levels.

Implementation Method 1

modulating a polarization state of the FeFET device in response to programming pulses applied to the FeFET device from the word line

Methodology Applied

Scientific EffectPolarization switching: Polarisation

Implementation Method 2

The select transistor comprises a ferroelectric field-effect transistor (FeFET) device

Methodology Applied

Scientific EffectFerroelectric effect:

Implementation Method 3

the modulation of the polarization state of the FeFET device causes a modulation of a programming current for tuning a conductance of the resistive memory device

Methodology Applied

Scientific EffectVoltage-controlled current modulation:

Data Source

PatentUS11948618B2Non-volatile analog resistive memory cells implementing ferroelectric select transistors

Publication Date: 2024.04.02 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has a tunable conductance. The select transistor is a ferroelectric field-effect transistor (FeFET) device which includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to the first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.