Analog Memory Device With Multi-Sensitivity Cells For Neural Weights
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Solution Overview
Problem
Existing memory devices are inadequate for storing analog information effectively, particularly in neural networks and other non-volatile memory applications, due to insufficient programming and reading sensitivity, which limits their ability to mimic neuro-biological architectures and store synaptic weights.
Innovation Solution
A memory device with a three-dimensional array of memory cells, each having different programming sensitivity, allowing them to store analog information by responding uniquely to the same programming pulses, and a reading circuit to access and combine the analog information from multiple cells, extending the analog storage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If memory devices use traditional digital storage methods with binary states, then the device structure remains simple and manufacturing is easier, but the programming and reading sensitivity is insufficient for analog storage applications
Solution Approach 1:
The patent applies parameter changes by transitioning from binary digital states to multi-level analog states in memory cells. By varying the resistance, capacitance, or charge parameters continuously rather than in discrete binary levels, the memory device achieves higher programming and reading sensitivity required for analog storage applications while maintaining compatibility with existing memory cell structures
Solution Approach 2:
The patent introduces an additional dimension of storage by implementing three-dimensional stacked memory architectures. By stacking multiple memory cell layers vertically and using selective readout circuits, the system can distinguish and read analog values from individual cells in the stack, thereby increasing measurement precision without proportionally increasing the footprint area
2Adaptability or versatility
If memory devices are designed for digital binary storage, then manufacturing processes are simpler and more成熟, but they cannot effectively store or retrieve analog information for neural network applications
Solution Approach 1:
The patent implements universality by designing memory cells that can operate in multiple modes - digital binary mode for traditional applications and analog mode for neural network applications. The same physical memory cell structure supports both discrete 0/1 states and continuous analog values, allowing a single manufacturing process to produce devices suitable for both digital and analog workloads
Solution Approach 2:
The patent uses parameter changes to enable analog storage capability by modifying the readout and programming circuitry to detect and manipulate continuous parameter ranges rather than discrete binary levels. By adjusting voltage, current, or time parameters during programming and using sensitive detection circuits for reading, the memory device can store and retrieve analog information representing synaptic weights in neural networks
3Measurement precision
If memory devices use standard read circuits for digital data, then the circuit design is simpler, but the reading sensitivity is insufficient to distinguish subtle analog differences between memory cells
Solution Approach 1:
The patent introduces intermediary readout circuits that act as mediators between the memory cells and the digital processing system. These intermediary circuits include differential amplifiers, sense amplifiers, or analog-to-digital converters that enhance the reading sensitivity by detecting subtle analog differences between memory cells and converting them into usable signals, thereby improving measurement precision without requiring complete redesign of the entire system
Data Source
AI summary
Methods, systems, and devices for analog storing information are described herein. Such methods, systems and devices are suitable for synaptic weight storage in electronic neuro-biological mimicking architectures. A memory device may include a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality. Memory cells may be provided on different decks of a multi-deck memory array. A storage element material of a respective memory cell may have a thickness and/or a composition different from another thickness or composition of a respective storage element material of another respective memory cell on a different deck in the multi-deck memory array. The memory device may further include reading circuitry configured to analogically read respective information programmed in the respective memory cells and to provide an output based on a combination of the respective information analogically read from the respective memory cells.