PCM Drift Compensation via Sequential Pulse Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase change memory (PCM) technology faces challenges in resistance drift, particularly in neuromorphic computing, where the resistance difference between states is small, affecting the reliability of multilevel-cell storage and requiring a drift coefficient of less than 0.005, which conventional techniques have not adequately addressed.
Innovation Solution
An analog phase change memory array with control circuitry that sends identical pulses to PCM resistors sequentially to compensate for resistance drift, using external resistors to adjust pulse heights and frequencies, ensuring consistent correction across the array without needing to read resistor values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PCM is used for multilevel-cell storage in neuromorphic computing, then the resistance difference between states is small enabling multiple resistance levels, but the sensing margin between adjacent resistance levels is reduced
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the reference resistance value used for comparison. Instead of using a fixed reference, the system modifies the reference resistance parameter to adapt to drift conditions, thereby maintaining adequate sensing margin while preserving multiple resistance levels for neuromorphic computing applications
2Device complexity
If PCM resistance drift is allowed to occur naturally, then the drift coefficient remains at conventional levels, but the reliability of multilevel-cell storage is seriously affected
Solution Approach 1:
The patent implements feedback by continuously monitoring the resistance drift in PCM cells and using this information to dynamically adjust the reference resistance value. This closed-loop feedback mechanism ensures that the sensing margin is maintained despite drift, thereby preserving storage reliability without requiring complex compensation hardware
Solution Approach 2:
The system changes the reference resistance parameter dynamically based on observed drift conditions. By adjusting this parameter rather than attempting to prevent drift entirely, the system maintains reliable operation while avoiding the need for complex compensation mechanisms
3Loss of time
If neural network training is performed for long durations, then accurate results can be achieved, but PCM drift mixes adjacent resistance states during the training period
Solution Approach 1:
The patent applies preliminary action by pre-establishing a dynamic reference resistance mechanism that proactively compensates for drift before it causes data corruption. This preliminary setup allows long training durations to proceed without risking resistance state mixing, as the reference continuously adapts to drift conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces resistance drift, maintaining the reliability of multilevel-cell storage in neuromorphic applications by stabilizing resistance levels, thereby enhancing the performance and accuracy of neuromorphic computing systems.
Implementation Method 1
Phase change memory (PCM) is memory that can store information while power is off. This memory is referred to as such because of its ability to switch from a disorderly (or amorphous) state to an orderly (or crystalline) one very quickly.
Implementation Method 2
control circuitry configured to send, using the first lines and second lines, a same set pulse through the at least one device to a plurality of individual phase change memory resistors in the phase change memory array sequentially once every period
Data Source
AI summary
An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.