Dynamic Verification Relaxation for Non-Volatile Memory Programming
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Solution Overview
Problem
Non-volatile memory devices face challenges in programming and erasing memory cells due to conflicting requirements between programming/erasure time and readout reliability, with slower cells requiring relaxed verification conditions that can degrade overall device performance.
Innovation Solution
Implementing a method where a demanding verification condition is applied initially, followed by relaxation after a predefined number of iterations, allowing for successful programming/erasure of majority cells while accommodating slower cells with a relaxed condition, and adjusting verification thresholds and permitted counts based on ECC correction capability and cycle counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a demanding verification condition is applied throughout the programming/erasure process, then readout reliability is improved, but programming/erasure time increases and slower cells may fail to complete the operation
Solution Approach 1:
The verification condition is made dynamic by transitioning from a demanding verification condition in initial iterations to a relaxed verification condition in subsequent iterations. This allows the system to adapt the verification strictness based on the progression of the programming or erasure operation, ensuring reliable programming while accommodating slower cells and reducing overall operation time.
Solution Approach 2:
The demanding verification condition is applied preliminarily in the initial iterations to ensure that most cells are properly programmed or erased. After a predefined number of iterations, the verification condition is relaxed to accommodate slower cells that may not have completed the operation yet, thereby reducing the total programming/erasure time while maintaining readout reliability for the majority of cells.
2Productivity
If a relaxed verification condition is applied to accommodate slower cells, then programming/erasure time is reduced, but readout reliability degrades
Solution Approach 1:
The verification condition dynamically transitions from demanding to relaxed based on the iteration count. This dynamic adjustment allows the system to maintain high readout reliability for the majority of cells that complete programming/erasure under the demanding condition, while still accommodating slower cells through the relaxed condition in later iterations, thus improving overall productivity without significantly compromising reliability.
Solution Approach 2:
The programming/erasure process is segmented into two phases: an initial phase with demanding verification conditions that ensures reliable programming for most cells, and a subsequent phase with relaxed verification conditions that accommodates slower cells. This segmentation allows the system to optimize for both reliability and productivity by applying different verification strictness to different time periods of the operation.
3Reliability
If demanding verification conditions are applied continuously, then readout reliability is maintained, but memory cells experience over-stress reducing device lifespan
Solution Approach 1:
The verification condition is made dynamic to reduce over-stress on memory cells. By transitioning from a demanding verification condition to a relaxed verification condition after a predefined number of iterations, the system maintains readout reliability for cells that have been properly programmed or erased while reducing the stress applied to slower cells that may not complete the operation, thereby extending device lifespan.
Solution Approach 2:
The demanding verification condition is applied preliminarily only for a predefined number of iterations to ensure proper programming/erasure of most cells. After this preliminary phase, the verification condition is relaxed to reduce over-stress on memory cells, particularly slower cells that continue to undergo programming/erasure, thus preserving device lifespan while maintaining adequate readout reliability.
Data Source
AI summary
A method for data storage includes setting a plurality of memory cells to hold respective target analog values, by applying to the memory cells a sequence of iterations, each iteration includes attempting to set the target analog values and then verifying whether the target analog values have been reached in accordance with a verification condition. After applying a predefined number of the iterations, the verification condition is relaxed and a condition of whether the target analog values have been reached in accordance with the relaxed verification condition is verified.