Adaptive Refresh Staggering for Memory Power Management
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Solution Overview
Problem
The existing PCIe links face limitations in managing high-bandwidth and low-latency memory access, particularly in environments with large shared memory pools and devices, leading to high power consumption and electrical noise issues during refresh operations in CXL-based systems.
Innovation Solution
Adaptive refresh staggering is implemented by programming delays between the initiation of refresh operations for each die in a multi-die package, reducing peak current draw and power consumption by staggering the start of refresh operations across dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed simultaneously on all memory arrays, then data retention is maintained, but peak power consumption and electrical noise increase
Solution Approach 1:
The patent segments the memory system into multiple memory arrays that can be refreshed independently. By dividing the refresh operation into separate units (individual memory arrays rather than a single simultaneous operation), the system maintains data retention while enabling staggered refresh timing to reduce peak power consumption and electrical noise.
Solution Approach 2:
The patent implements periodic refresh operations with controlled timing intervals between different memory arrays. Instead of simultaneous refresh, the system performs periodic refresh cycles where different arrays are refreshed at different times, maintaining data retention requirements while reducing peak power demand and electrical interference.
2Reliability
If refresh operations are performed simultaneously on all memory arrays, then data retention is maintained, but electrical noise increases
Solution Approach 1:
The patent segments the memory system into multiple memory arrays that can be refreshed independently. By dividing the refresh operation into separate units, the system maintains data retention while enabling staggered refresh timing to reduce peak power consumption and electrical noise.
Solution Approach 2:
The patent implements periodic refresh operations with controlled timing intervals between different memory arrays. Instead of simultaneous refresh, the system performs periodic refresh cycles where different arrays are refreshed at different times, maintaining data retention requirements while reducing peak power demand and electrical interference.
3Productivity
If multiple memory arrays are refreshed at the same time, then refresh efficiency is high, but power delivery network complexity increases
Solution Approach 1:
The patent segments the memory system into multiple memory arrays that can be refreshed independently. By dividing the refresh operation into separate units, the system maintains data retention while enabling staggered refresh timing to reduce peak power consumption and electrical noise.
Solution Approach 2:
The patent introduces dynamic control over refresh timing for different memory arrays. The system can adaptively adjust when each array is refreshed based on operational requirements, allowing the power delivery network to handle lower peak demands and reducing overall system complexity.
4Use of energy by moving object
If refresh operations are staggered across multiple dies, then peak current draw is reduced, but refresh latency increases
Solution Approach 1:
The patent segments the memory system into multiple memory arrays that can be refreshed independently. By dividing the refresh operation into separate units, the system maintains data retention while enabling staggered refresh timing to reduce peak power consumption and electrical noise.
Solution Approach 2:
The patent implements periodic refresh operations with controlled timing intervals between different memory arrays. Instead of simultaneous refresh, the system performs periodic refresh cycles where different arrays are refreshed at different times, maintaining data retention requirements while reducing peak power demand and electrical interference.
Data Source
AI summary
Described apparatuses and methods relate to adaptive refresh staggering for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a memory device can include logic that can be programmed to stagger the start of refresh operations for each die upon receiving a command to enter a lower-power mode, such as self-refresh. The staggered start can be implemented at a channel level, a package level, or both. The programming sets a delay for each die so that initiation of refresh operations is staggered. Thus, a first die can initiate refresh operations when a command to enter the lower-power mode is received (e.g., approximately zero delay). However, initiation of refresh operations for subsequent dies (e.g., “after” the first die) is delayed, which can reduce peak current draw and power consumption.