Digital Storage TRIZ Cases

A repair circuit generates column repair signals to access normal and redundancy lines simultaneously.

Segmented redundant driver circuits in memory chip I/O pads scale capability to resolve performance drops from increased storage capacity.

Shared holding transistors in the word line driver reduce layout area and signal resistance, resolving speed delays caused by increased memory cell counts.

A spin-orbit torque assisted magnetic random access memory bit cell array uses a spin-hall conductive layer to generate deterministic switching currents.

A proactive noise suppression system correlates IC event sequences with anti-noise signatures to generate counter signals in power supply networks.

Dynamic control of write current and voltage minimizes heat generation after resistance state changes, preventing write errors in resistance change memory.

Segmented refresh operations combine low-current recovery pulses with periodic data re-writes to maintain reliability while reducing power consumption.

Peripheral memory circuitry stores recursive results in posit format to reduce rounding errors and overflow while maintaining system compatibility.

A hybrid memory cell uses capacitance for fast data storage in dynamic mode and resistive states for low-power non-volatile storage.

Variable resistive elements in a 4T2R ternary CAM cell limit current flow during read operations to reduce read disturb and minimize circuit area.

Hardware accelerator architecture uses a data management unit to provide low-latency parallel random memory access for processing sparse matrix operations.

A resistive processing unit applies input vectors to perform analog matrix-vector multiplication and obtains output vectors for weight determination.

Shared bit and word lines in MRAM arrays use selection transistors with buffering to manage capacitance.

Propagation circuitry routes read data through sub-array columns using control signals, reducing leakage current impact and power consumption.

A sense amplifier circuit uses dual inverters to equalize bit line voltages in semiconductor memory devices.

A quantum-inspired parallel annealing processor uses memristor crossbar arrays to compute gradients via analog conductance.

A discharging circuit applies ground voltage to non-selected lines in phase change memory arrays.

A stepped gate structure in static random-access memory layouts releases accumulated electrical charge through adjacent complementary diffusion regions.

Adaptive refresh staggering segments memory arrays into independent units, reducing peak power consumption and electrical noise during lower-power mode entry.

A phase change memory element uses a three-dimensional groove structure to position the top electrode directly on the recording layer growth initiation surface.

A mixed mode memory cell uses a selection circuit to switch between volatile and non-volatile storage modes.

A semiconductor device manages redundant addresses using an address storage unit that deletes identical entries during reset operations.

A semiconductor internal voltage generation circuit groups banks to reduce control signal complexity.

A converting unit translates address and control signals between SRAM and SDRAM interfaces for a unified memory array.

Common reference lines average Vref circuit outputs while fusible links isolate defective units, reducing bit error rates in MRAM arrays.

A multi-chip memory device uses a command tracker to determine execution of address-less commands based on operational history.

Merging multiple latches into one structure reduces internal pixel area, expanding dynamic range in high frame rate sensors.

A dummy global read line tracks precharge completion to prevent contention and reduce dynamic power consumption in high-speed SRAM.

Endpoint replay refines data strobe signal calibration by narrowing the search range around initial delay values.

A semiconductor memory device uses variable resistance patterns coupled to memory cells to isolate defective components and block leakage current paths.

Shorting the reference cell variable resistor eliminates dispersion, increasing main cell sensing margin.

Patsnap Eureka TRIZ case analyzes how altering logical value distributions reduces energy consumption and disturbance effects during RRAM operations.

Latency signal generation unit samples commands via ring counters to reduce layout area and access time for multiple CAS latency types.

Shield lines mitigate bit line noise in 2T2C regions while ground potential handles 1T1C areas, avoiding extra wiring layers.

Dual amplifier ReRAM sensing circuits reduce high-resistance read latency by stabilizing voltage levels faster through preliminary current amplification.

NOC-CLSA reduces input capacitance and offset voltage in MRAM sensing circuits.

Nested count value memory cells identify aggressor rows to perform targeted refresh operations that mitigate row hammer data degradation.

A control circuit adjusts nonvolatile memory read voltages based on elapsed programming time to maintain data integrity.

Digit line multiplexing in sense amplifiers merges amplifier and latch stages, reducing area utilized by sense components while maintaining read margin.

A clean data strobe signal generating circuit uses a gate signal to mask unknown sections in read interface devices.

Shorting neighboring access transistors along word lines pools drive currents to boost signal strength.

Buffer control circuit adjusts enable period based on command latency signals.

A dynamically adjustable memory pipeline reconfigures internal stages to match access patterns.

A nonvolatile bit cell uses ferroelectric capacitors to store state information without continuous power.

A refresh control circuit selectively activates specific data blocks to target affected word lines during row hammer events.

Segmenting global read bit lines into selected and unselected groups reduces electrical power consumption by avoiding unnecessary pre-charging cycles.

A memory device uses a fly word line to selectively activate half of the row cells during read operations.

A semiconductor device structure manages data retention by switching potential control lines between levels to manage power supply potentials.