Mixed Mode Memory Cell Volatile Non-Volatile Switching
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Solution Overview
Problem
Current memory technologies, such as SRAM and DRAM, are volatile, losing data when power is turned off, limiting their adaptability and compatibility with devices requiring different storage modes.
Innovation Solution
A mixed mode memory cell with a reading and writing component group, storage circuit, and selection circuit that can operate in either volatile or non-volatile storage modes based on a selection voltage, utilizing phase change elements and MOSFETs to control data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory (SRAM/DRAM) is used, then high speed and low power consumption are achieved, but data is lost when power is turned off
Solution Approach 1:
The memory cell employs dynamic reconfiguration of transistor connections through the selection circuit. The first and second transistors can be dynamically connected to different nodes (first node/ground or second node/ground) based on the selection signal, allowing the memory to switch between volatile and non-volatile operational modes. This dynamic structural change enables the system to adapt its data retention characteristics while maintaining high-speed performance when needed.
Solution Approach 2:
The invention changes the operational parameters of the memory cell by controlling the selection signal that determines the connection state of the transistors. When the selection signal is at a first level, the transistors connect to the first node enabling volatile mode with fast access. When the selection signal is at a second level, the transistors connect to the second node enabling non-volatile mode with data retention capability. This parameter change allows the memory to optimize between speed and reliability based on operational requirements.
2Reliability
If non-volatile storage mode is used, then data retention is improved, but adaptability to different device requirements is reduced
Solution Approach 1:
The memory cell is designed with multi-functionality through the inclusion of a selection circuit that enables it to operate in multiple modes. The same memory cell structure can function as volatile memory, non-volatile memory, or a combination of both, depending on the selection signal. This universal design allows a single memory device to serve diverse application requirements without needing separate dedicated memory types, thereby improving adaptability while maintaining data retention capabilities.
Solution Approach 2:
The dynamic reconfiguration capability allows the memory to adapt its characteristics in real-time based on system requirements. The selection circuit enables flexible switching between operational modes, making the memory system adaptable to different device requirements whether fast volatile access or reliable non-volatile storage is needed, all within the same physical hardware architecture.
3Adaptability or versatility
If different memory types are designed for different storage modes, then specific device requirements are met, but development cost increases
Solution Approach 1:
The invention merges the functionality of volatile and non-volatile memory types into a single unified memory cell structure. By integrating the selection circuit with the standard memory transistor array, the design combines multiple memory functionalities without requiring separate physical memory devices. This merging approach reduces development costs, simplifies manufacturing processes, and eliminates the need for multiple memory types while still providing adaptability to match various device requirements through software-controlled mode selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high adaptability by allowing data retention in either mode without changing the memory circuit design, reducing development costs and matching various device requirements.
Implementation Method 1
the first transistor and the second transistor are respectively a phase change element and a transistor
Data Source
AI summary
A mixed mode memory cell comprises a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line and two bit lines, wherein the two bit lines respectively transmit two data signals. The storage circuit is electrically coupled to the reading and writing component group. The selection circuit is electrically coupled to the reading and writing component group and the storage circuit, and configured to control the storage circuit to operate in a volatile storage mode or a non-volatile storage mode based on a selection voltage.