Sense Amplifier Circuit for Semiconductor Memory Devices
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Solution Overview
Problem
In semiconductor memory devices with open bit line structures, the increased bit line loading and capacitance imbalance between edges of the memory cell array lead to reduced charge sharing voltage, causing sensing failures due to suboptimal pre-charge levels.
Innovation Solution
A semiconductor memory device with a sense amplifier circuit configuration that includes a first and second inverter, where the first inverter is activated independently during a pre-sense period and both inverters are activated simultaneously after the pre-sense period, ensuring optimal bit line voltage equalization and charge sharing, thereby minimizing the impact of loading mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If balance capacitors are used to replace leftmost and rightmost memory cell sub-arrays, then chip size is reduced, but loading mismatch between bit lines occurs causing sensing failures
Solution Approach 1:
The patent applies preliminary action by performing bit line equalization before the sensing operation. The equalizer circuit pre-charges the bit lines to VA/2 target level during a pre-charge period, ensuring that even with loading mismatches from balance capacitors, the bit lines start at the optimal voltage level for subsequent charge sharing and sensing operations.
Solution Approach 2:
The patent changes the operating parameters by introducing separate control signals for the equalizer and sense amplifier circuits. The equalizer is activated during a pre-charge period to establish optimal voltage levels, while the sense amplifier is activated during the sensing period. This temporal separation of operations allows the system to adapt to loading mismatches by adjusting the pre-charge voltage parameter to compensate for capacitor loading effects.
2Quantity of substance
If open bit line structure is used, then bit line loading is reduced, but loading mismatch at edges causes suboptimal pre-charge levels
Solution Approach 1:
The patent introduces an equalizer circuit as an intermediary between the bit lines and the sense amplifier. This equalizer acts as a mediator that actively manages the bit line voltage levels during the pre-charge period, compensating for the loading effects of balance capacitors and ensuring accurate VA/2 pre-charge levels are achieved despite the open bit line structure.
3Speed
If both inverters are activated simultaneously, then sensing speed is improved, but pre-charge level accuracy deteriorates due to loading mismatch
Solution Approach 1:
The patent segments the sensing operation into two distinct phases: a pre-charge period where only the equalizer is activated to establish accurate voltage levels, and a sensing period where both the equalizer and sense amplifier are activated simultaneously for high-speed sensing. This temporal segmentation allows the system to optimize for precision during pre-charge and for speed during sensing, resolving the contradiction between these two requirements.
Data Source
AI summary
A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.