Oxide Semiconductor Transistor Data Retention Circuit
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Solution Overview
Problem
Semiconductor devices with oxide semiconductors face challenges in retaining data for long periods without additional power supply circuits, as normally-off transistors struggle with low on-state current when high power is applied, and normally-on transistors have difficulty maintaining low drain current at low power supply potentials.
Innovation Solution
A semiconductor device structure that includes a transistor capable of controlling conduction between terminals based on a gate signal, a volatile memory circuit, and a capacitor with a potential control line, allowing data retention by switching the potential control line between levels to manage power supply potentials, eliminating the need for additional power supply circuits to generate negative or high potentials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a normally-off OS transistor is used to retain data for long time, then data retention is improved, but on-state current becomes insufficiently large when high power supply potential is supplied
Solution Approach 1:
The patent changes the electrical parameters of the OS transistor by controlling the potential difference between gate and source. By supplying a gate potential that is lower than the source potential (negative Vgs), the transistor operates in a state where it can maintain low off-state current for data retention while still achieving sufficient on-state current when needed for data writing operations.
2Power
If a normally-on OS transistor is used to obtain large on-state current, then data writing speed is improved, but drain current cannot be kept small when low power supply potential is supplied
Solution Approach 1:
The patent makes the transistor's operational state dynamic by controlling the gate potential relative to the source potential. The transistor can switch between normally-off state (for data retention) and normally-on state (for data writing) by adjusting the gate-source voltage, allowing flexible adaptation to different operational requirements without additional power supply circuits.
3Power
If additional power supply circuit is added to generate negative potential or high potential, then transistor performance is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent makes the existing power supply circuit serve multiple functions: it provides both the regular power supply potential and the control potential for the gate terminal. By utilizing the same power supply circuitry for dual purposes, the patent avoids the need for additional dedicated power supply circuits, thereby reducing circuit area and power consumption while still achieving the desired transistor performance.
Data Source
AI summary
A normally-off state of an OS transistor is maintained or an on-state current thereof is increased without additionally generating a positive potential or a negative potential. When data is written to a node connecting an OS transistor and a capacitor, a potential supplied to the other side of the capacitor is set to an L level, and when the data is retained, the potential is switched from the L level to an H level. In addition, a power switch for a volatile memory circuit is provided on a low power supply potential side so that the supply of a power supply voltage can be stopped. Accordingly, at the time of data retention, a source and a drain of the OS transistor can be set at a high potential, whereby the normally-off state can be maintained and the on-state current can be increased.