NMOS Offset Canceling Current Latched Sense Amplifier
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Solution Overview
Problem
Magnetic random access memory (MRAM) faces a read disturbance problem due to the shared current path for write and read operations, leading to reduced sensing margin and switching speed as technology scales, necessitating a solution to prevent incorrect data readings and improve sensing speed.
Innovation Solution
The implementation of an NMOS offset-cancelling current latched sense amplifier (NOC-CLSA) with reduced input capacitance and output capacitance mismatch, coupled with an offset-canceling dual stage sensing circuit, which cancels process variations and reduces sense amplifier offset voltage, thereby enhancing sensing margin and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sensing current is reduced to prevent read disturbance in scaled MRAM, then read disturbance is prevented, but the sensing margin is reduced
Solution Approach 1:
The sense amplifier pre-charges its internal nodes to a predetermined voltage level before the sensing operation begins. This preliminary action ensures that when the reduced sensing current is applied, the amplifier starts from a known state and can still detect the resistance difference effectively, maintaining sensing margin even with lower current
Solution Approach 2:
The invention changes the operating parameters of the sense amplifier by adjusting the pre-charge voltage levels and timing to optimize performance at reduced sensing currents. By modifying these parameters, the amplifier maintains adequate sensing margin while operating with the lower currents required to prevent read disturbance in scaled devices
2Reliability
If the sensing current pulse width is reduced to prevent read disturbance, then read disturbance is prevented, but the switching speed of MTJ is reduced
Solution Approach 1:
The sense amplifier employs dynamic operation with rapid switching between pre-charge and sensing phases. The internal transistors switch quickly to amplify the small voltage differences generated by the short sensing current pulse, compensating for the reduced pulse width and maintaining adequate sensing speed despite the shortened current application time
3Measurement precision
If conventional NMOS offset canceling voltage latched sense amplifier is used, then offset voltage is canceled, but input capacitance and output capacitance mismatch are large
Solution Approach 1:
The sense amplifier is divided into separate functional blocks: pre-charge circuitry, sensing circuitry, and latch circuitry. Each block is optimized independently, allowing the input stage to have minimal capacitance while the latch provides the offset cancellation function. This segmentation reduces the overall input and output capacitance mismatch compared to integrated conventional designs
Solution Approach 2:
The invention introduces intermediate buffering stages between the input differential pair and the latch circuit. These intermediate stages act as mediators that transfer the differential signal with minimal capacitance loading, reducing the impact of latch capacitance on the input stage and thereby reducing input capacitance and mismatch
4Area of moving object
If MTJ scaling is increased, then device area is reduced, but the sensing current must be reduced which reduces sensing margin
Solution Approach 1:
The sense amplifier pre-charges its differential input nodes to a voltage level that maximizes the voltage swing available for detection. This preliminary action ensures that even when the sensing current is reduced due to MTJ scaling, the amplifier can still detect the smaller voltage differences with adequate margin by starting from an optimized initial state
Data Source
AI summary
A resistive memory sensing method includes sensing outputs of an offset-cancelling dual stage sensing circuit (OCDS-SC) by an NMOS offset-cancelling current latched sense amplifier circuit (NOC-CLSA). The NOC-CLSA is configured with a reduced input capacitance and a reduced offset voltage. Input transistors of the NOC-CLSA are coupled between latch circuitry and ground. A first phase output of the OCDS-SC is stored by the NOC-CLSA during a pre-charge step of the NOC-CLSA operation. A second phase output of the OCDS-SC is stored by the NOC-CLSA during an offset-cancelling step of the NOC-CLSA operation. By pipelining the OCDS-SC and NOC-CLSA, a sensing delay penalty of the OCDS-SC is overcome.