Semiconductor Memory Noise Mitigation via Shield Lines and Ground Potential
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reducing noise between bit lines, particularly when both 1T1C and 2T2C memory regions coexist, leading to increased manufacturing costs and chip area, as existing methods either require additional wiring layers or cannot be applied to complementary reading scenarios.
Innovation Solution
A semiconductor memory design with separate memory regions for reference signal and complementary reading, where one upper bit line is fixed to ground potential in the 1T1C region and shield lines are used in the 2T2C region, all within the same wiring layer, to mitigate noise without increasing device size or complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If bit lines are made to intersect to evenly distribute noise, then noise distribution is improved, but the number of wiring layers increases and manufacturing cost increases
Solution Approach 1:
The bit lines are divided into multiple groups (first bit lines, second bit lines, third bit lines) with different routing patterns. First bit lines extend in a first direction, second bit lines extend in a second direction, and third bit lines extend in the first direction again. This segmentation allows noise to be distributed across different spatial directions without requiring bit lines to intersect, thereby reducing the number of wiring layers needed while still achieving even noise distribution.
Solution Approach 2:
Instead of using vertical intersections to distribute noise, the patent distributes noise by utilizing horizontal spacing and directional differentiation. The bit lines are arranged in parallel groups extending in alternating directions, creating noise distribution through dimensional separation in the planar layout rather than through vertical layering via intersections.
2Object-affected harmful factors
If deselected bit lines are set to ground potential to prevent noise, then noise between bit lines is reduced, but this method cannot be applied to complementary reading memory regions
Solution Approach 1:
Different noise mitigation strategies are applied to different memory regions based on their specific requirements. In the first memory region (1T1C type), deselected bit lines are connected to ground potential. In the second memory region (2T2C type with complementary reading), shield lines are provided between adjacent bit lines. This local differentiation allows each region to use the most appropriate noise reduction method for its architecture.
Solution Approach 2:
Shield lines are introduced as intermediary elements between adjacent bit lines in the second memory region. These shield lines act as mediators that block or reduce the electromagnetic coupling between bit lines during complementary reading operations, providing noise mitigation without requiring bit lines to be set to ground potential.
3Object-affected harmful factors
If additional wiring layers are added to reduce noise, then noise mitigation is improved, but chip area increases and manufacturing cost increases
Solution Approach 1:
The patent employs dynamic control of bit line potentials through selective connection to ground potential in the first memory region. During operation, deselected bit lines are dynamically connected to ground only when needed for noise reduction, while remaining operational bit lines maintain their signal-carrying function. This dynamic approach achieves noise mitigation without permanently increasing chip area with additional wiring structures.
4Quantity of substance
If bit lines are densely packed to increase memory density, then storage capacity is improved, but noise between adjacent bit lines increases
Solution Approach 1:
The patent introduces asymmetry in the routing directions of different bit line groups. First bit lines extend in a first direction, while second bit lines extend in a second direction perpendicular to the first. This asymmetric arrangement breaks the uniform parallel pattern, increasing the effective spacing between adjacent bit lines from different groups and reducing capacitive coupling and noise, thereby allowing higher memory density without proportional noise increase.
Data Source
AI summary
A semiconductor memory includes j×k first memory cells, j upper bit lines, (½)j sense amplifiers, j×k lower first bit lines, k first word lines, k pairs of plate lines, each pair having first and second plate lines, each being connected to odd-numbered and even-numbered first memory cells of one of the k columns, a pair of discharge signal lines having a first discharge signal line and a second discharge signal line respectively connecting two of the j upper lines in each sense amplifier to a prescribed potential, j×m second memory cells, j lower second bit lines, m second word lines, m third plate lines each connected to the j second memory cells of one of the m columns, and j shield lines each provided at positions respectively corresponding to the j upper bit lines, which are parallel to one another.