SRAM Global Read Line Precharge Tracking via Dummy Line
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Solution Overview
Problem
High-speed static random access memory (SRAM) architectures face challenges in meeting margin conditions for precharging global read lines, leading to functional failures and high dynamic power consumption across various pressure, voltage, and temperature conditions.
Innovation Solution
A memory circuit with N banks of memory cells, each with M columns, featuring sense amplifiers, a global read precharge tracking control circuit, and a read delay circuit that ensures precharge completion before sense amplifier enable, eliminating contention and optimizing cycle time and dynamic power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If precharge of global read lines is performed before sense amplifier enable, then functional reliability is improved, but device complexity increases due to additional tracking control circuits
Solution Approach 1:
A dummy global read line is created as a copy of the actual global read lines. This dummy line travels through the same physical path and experiences identical PVT variations. A tracking control circuit monitors the precharge status of the dummy line and uses this information to control the precharge of the actual global read lines, ensuring they are properly charged without requiring direct monitoring of each individual line.
Solution Approach 2:
The tracking control circuit acts as an intermediary between the dummy global read line and the actual global read lines. It receives the track dummy global read line signal, processes it to determine precharge completion, and generates appropriate control signals to ensure the actual global read lines are precharged before sense amplifier operation begins.
2Reliability
If global read lines precharge is completed before sense amplifier discharge, then contention on global read lines is avoided, but cycle time increases
Solution Approach 1:
The system implements feedback through the track dummy global read line signal that returns from halfway to the top of the SRAM. This feedback mechanism allows the tracking control circuit to monitor the actual precharge progress in real-time and adjust control signals accordingly, ensuring precharge completion is detected as quickly as possible without premature operation.
Solution Approach 2:
The precharge operation is initiated in advance before the sense amplifier enable signal arrives. The tracking control circuit is designed to complete the precharge of global read lines before the sense amplifiers begin their discharge operation, ensuring that the lines are ready to receive data without contention while minimizing the overall cycle time through efficient timing control.
3Adaptability or versatility
If margin-free tracking is achieved across PVT variations, then robustness is improved, but device complexity increases due to additional tracking circuits
Solution Approach 1:
The dummy global read line serves as a physical copy that experiences identical pressure, voltage, and temperature variations as the actual global read lines. By monitoring this copy through the tracking control circuit, the system achieves margin-free tracking across all PVT conditions without requiring multiple sensors or complex monitoring mechanisms for each individual line.
Solution Approach 2:
The tracking control circuit serves multiple functions: it monitors the dummy global read line signal, determines precharge completion status, generates control signals for the actual global read lines, and ensures proper timing coordination. This multi-functional approach achieves robust PVT adaptation without proportionally increasing device complexity.
Data Source
AI summary
In embodiments of the invention, a memory circuit includes a static random access memory (SRAM), rows of M sense amplifiers, a global read precharge tracking control circuit controlling a precharge of global read lines, a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits, and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output tracking circuit and performing a fixed delay tracking of a read operation in a read cycle. A dummy global read line is coupled to the global read precharge tracking control circuit and returns from a half way to the top of the SRAM forming a tracking dummy global read line that determines a completion of the precharge of the global read lines before the sense amplifiers start discharging the global read lines in the read cycle.