Semiconductor Memory Latency Signal Generation Unit
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in handling high-speed DRAM with multiple types of CAS latency, leading to increased latency chains, layout area, and access time, which restricts data access speed.
Innovation Solution
A semiconductor memory device design that includes a command buffer, clock buffer, delay measurement and initialization unit, delay locked loop, latency signal generation unit, and data output buffer, which samples and transmits command signals using ring counters and transmission units to manage latency effectively, reducing the need for additional delay chains and optimizing clock signal delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple delay chains are added to support multiple CAS latency types, then adaptability is improved, but device complexity and layout area increase
Solution Approach 1:
The patent implements a universal delay chain structure that can be configured to provide different latency values (CL5, CL7, CL9, CL11) through a single multi-functional unit. The delay chain uses a unified architecture with configurable delay elements that can be programmed or selected to achieve different CAS latency requirements, eliminating the need for separate dedicated delay chains for each latency type.
Solution Approach 2:
The patent introduces dynamic configurability to the delay chain, allowing it to adapt its delay characteristics based on the required CAS latency type. Through dynamic control signals and selectable paths, the same physical hardware can dynamically adjust its effective delay time to match different latency requirements, transforming a static structure into a dynamic, adaptable system.
2Adaptability or versatility
If multiple delay chains are added to support multiple CAS latency types, then adaptability is improved, but layout area increases
Solution Approach 1:
The patent implements a universal delay chain structure that can be configured to provide different latency values (CL5, CL7, CL9, CL11) through a single multi-functional unit. The delay chain uses a unified architecture with configurable delay elements that can be programmed or selected to achieve different CAS latency requirements, eliminating the need for separate dedicated delay chains for each latency type.
Solution Approach 2:
The patent merges multiple functionally identical delay chains into a single shared resource. By combining the delay generation functionality into one unified structure that serves all CAS latency types, the physical layout area required is significantly reduced compared to having separate delay chains for each latency type.
3Adaptability or versatility
If delay chains are extended to cover all CAS latency types, then adaptability is improved, but access time increases
Solution Approach 1:
The patent introduces dynamic configurability to the delay chain, allowing it to adapt its delay characteristics based on the required CAS latency type. Through dynamic control signals and selectable paths, the same physical hardware can dynamically adjust its effective delay time to match different latency requirements, transforming a static structure into a dynamic, adaptable system.
Solution Approach 2:
The patent prepares the delay chain in advance by pre-configuring delay elements and establishing ready-state paths for different CAS latency types. When a specific latency type is required, the system can quickly switch to the pre-prepared configuration, avoiding the need to build or extend delay chains during operation, thus minimizing access time overhead.
Data Source
AI summary
A semiconductor memory device includes a command buffer that receives an external command and outputs a first command signal, a clock buffer that receives an external clock signal and outputs a first internal clock signal, a delay measurement and initialization unit that receives the first internal clock signal and a fourth internal clock signal and responsively outputs a second internal clock signal and a plurality of delayed signals corresponding to a delay time between when the external clock signal is input and data is output, a delay locked loop that receives the second internal clock signal and outputs a third internal clock signal and the fourth internal clock signal, a latency signal generation unit that delays the first command signal by a delay time between when the second internal clock signal is input to the delay locked loop and when the third internal clock signal is output from the delay locked loop, and then outputs the delayed first command signal as a latency signal, in response to the second and third internal clock signals and the delayed signals, and a data output buffer that outputs the data in response to the latency signal and the third internal clock signal.