Pixel Counting Device Area Reduction via Latch Merging
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Solution Overview
Problem
Existing counting devices in sensors have a large size due to data flip-flops, which occupy significant internal pixel area, limiting the dynamic range and performance of image sensors, especially under high dynamic range and high frame rate conditions.
Innovation Solution
A counting method and device with a storage module and arithmetic module in cascade interconnection, where storage units store cumulative count values and end-around shift for calculation, reducing the area required by the counting circuit and improving dynamic range by replacing multiple latches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data flip-flops and multiple latches are used in the counting device, then the counting function is achieved, but the internal pixel area is significantly occupied
Solution Approach 1:
The patent merges multiple latches into a single latch structure. The counting device uses one latch to store the current count value and another latch to store the threshold value, replacing the traditional multi-latch configuration. This consolidation significantly reduces the area occupied by the counting device while maintaining the counting function through coordinated operation of the reduced latch set.
Solution Approach 2:
The latch structures are designed to perform multiple functions. The same latch circuits are used for both counting and threshold comparison operations. The latch outputs are fed back to control the switching transistor, enabling the counting device to function as both a counter and a threshold detector, eliminating the need for separate dedicated circuits for each function.
2Reliability
If more circuits are added to the pixel to achieve partial digitization, then the dynamic range is improved, but the pixel area is limited and cannot accommodate indefinitely increasing circuits
Solution Approach 1:
The patent combines the counting circuit and threshold comparison circuit into a single integrated pixel-level device. By merging these functions into one compact structure with reduced latch requirements, the design achieves partial digitization at the pixel level without proportionally increasing pixel area, thereby improving dynamic range within area constraints.
Solution Approach 2:
The patent changes the operational parameters of the counting device by using a reduced latch configuration and implementing feedback control through switching transistors. This parameter optimization allows the counting device to achieve higher dynamic range performance with fewer circuit elements, enabling better area efficiency while maintaining improved measurement precision.
3Area of stationary object
If the counting device area is reduced to optimize pixel area, then the pixel area is optimized, but the counting accuracy and dynamic range may be compromised
Solution Approach 1:
The patent merges the threshold comparison function with the counting function in a compact integrated device. The latch outputs directly control the switching transistor that regulates current flow, creating a feedback mechanism that maintains counting accuracy. This merged structure achieves area reduction while preserving measurement precision through efficient functional integration.
Solution Approach 2:
The counting device implements self-service through feedback control. The latch outputs are fed back to control the switching transistor, which automatically adjusts the current flow based on the count value. This self-regulating mechanism maintains counting accuracy without requiring additional external control circuits, enabling area reduction while preserving measurement precision.
Data Source
AI summary
A counting method, a counting device, and a counting system and a pixel array using the counting device are provided. The counting device includes a storage module, which comprises multiple storage units in cascade interconnection, the multiple storage units store a plurality of cumulative count values, the multiple storage units are configured as at least one group of storage units; an arithmetic module connected to a first group of storage units and a last group of storage units for calculation according to a received count value and an added cumulative count values input through the last group of the storage units so as to obtain a current added cumulative count values of corresponding objects, which is then output to the first group of the storage units in cascade interconnection.