Pre-charging Selected Global Read Bit Lines
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Solution Overview
Problem
Existing memory array technologies consume excessive electrical power due to the practice of pre-charging all global read bit lines at the end of a prior read operation, which is unnecessary for un-selected memory cells during a current read operation.
Innovation Solution
Selected global read bit lines corresponding to memory cells to be read are pre-charged at the beginning of a current read operation, while un-selected global read bit lines are not pre-charged, reducing electrical power consumption by avoiding unnecessary pre-charging and discharging of un-accessed bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all global read bit lines are pre-charged at the end of a prior read operation, then all bit lines are ready for the next read operation, but electrical power consumption increases
Solution Approach 1:
The patent divides the global read bit lines into two groups: selected bit lines (corresponding to memory cells to be read) and unselected bit lines. Only the selected bit lines are pre-charged, while unselected bit lines are left in their previous state. This segmentation allows the system to maintain read operation readiness for the required memory cells while avoiding unnecessary power consumption from charging all bit lines.
Solution Approach 2:
Instead of pre-charging all global read bit lines (excessive action), the patent applies pre-charging only to the subset of bit lines that are actually needed for the current read operation (partial action). This partial pre-charging approach eliminates wasted energy on unselected bit lines while ensuring that the necessary bit lines are properly prepared for reading.
2Adaptability or versatility
If all global read bit lines are pre-charged and discharged, then data reading is enabled for all memory cells, but unnecessary pre-charging of un-selected bit lines increases power consumption
Solution Approach 1:
The patent applies different treatment to different portions of the bit line system based on their selection status. Selected global read bit lines receive the pre-charging treatment necessary for proper read operation, while unselected bit lines are left unchanged. This local differentiation ensures that each bit line receives the appropriate level of preparation based on whether it is needed for the current operation, thereby eliminating wasteful energy consumption.
3Ease of operation
If read bit lines are pre-charged to high logical value, then data output is enabled, but pre-charging and discharging operations consume electrical power
Solution Approach 1:
The patent segments the bit line pre-charging operation into selected and unselected portions. Only the selected global read bit lines undergo the pre-charging and subsequent discharging cycle required for data output. By eliminating the pre-charging/discharge cycle for unselected bit lines, the system maintains full data output capability for the targeted memory cells while significantly reducing the energy consumption associated with these switching operations.
Data Source
AI summary
A circuit includes a signal generating circuit that generates a pre-charge signal based on a clock signal and a column select signal for a column of memory cells associated with the signal generating circuit. A first state of the pre-charge signal depends on a first state of the column select signal, and the first state of the column select signal corresponds to selection of the column of memory cells. The circuit also includes a charge circuit associated with the signal generating circuit and a first data line coupled to the charge circuit. The charge circuit charges the first data line in response to the first state of the pre-charge signal and allows the first data line to float in response to a second state of the pre-charge signal.