Pooling Transistor Drive Currents in Resistive Memory Arrays
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Solution Overview
Problem
The density of non-volatile memory fabrication is limited by the size of the access transistor, which restricts the current supplied to memory elements, necessitating designs that maximize current while maintaining unique programming and read access.
Innovation Solution
The method involves forming a memory structure with an array of resistive memory cells connected to bit and word lines, where rectifying elements and access transistors are configured in series, and neighboring transistors are shorted together along word lines to pool transistor drive currents, allowing increased current supply while maintaining individual memory element access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of the access transistor is reduced to increase memory density, then the area per memory cell is reduced, but the maximum current supplied to memory elements is reduced
Solution Approach 1:
The patent merges multiple access transistors (specifically two transistors per memory element) to work in parallel on the same bitline, combining their current driving capabilities while maintaining individual control through wordline selection. This allows the effective current supply to be doubled without increasing the area per memory cell proportionally, as the transistors share the same bitline infrastructure.
Solution Approach 2:
The patent introduces dual bitlines (BL0 and BL1) for each memory element, adding a dimensional aspect to the current path. By configuring transistors to switch between different bitlines based on wordline activation, the system achieves increased current capability without simply scaling up transistor size in the traditional planar dimension.
2Power
If multiple access transistors are combined to increase current supply, then the maximum current supplied to memory elements is increased, but the complexity of maintaining unique programming and read access increases
Solution Approach 1:
The patent segments the control function by assigning different wordlines (WL0, WL1, WL2, WL3) to control different transistor pairs, creating distinct access paths to each memory element. This segmentation allows independent programming and reading of each memory element even though multiple transistors share bitlines, as each wordline independently controls its associated transistors.
Solution Approach 2:
The patent uses wordlines as intermediary control elements that mediate between the control logic and the multiple access transistors. Each wordline acts as an independent mediator that can selectively activate or deactivate specific transistor pairs, enabling precise control over which memory elements are accessed despite the shared bitline infrastructure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the maximum current supplied to memory elements in non-volatile memory arrays, enhancing memory performance by pooling transistor drive currents while ensuring unique programming and read access to each element.
Implementation Method 1
configuring a rectifying element in series with each of the resistive memory devices at a second end thereof
Implementation Method 2
configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines
Implementation Method 3
forming a common connection configured to short neighboring access transistor devices together along a word line direction, in groups of two or more
Implementation Method 4
Phase change materials can be electrically switched between a generally amorphous, high resistance state and a generally crystalline, low resistance state
Data Source
AI summary
A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.