MRAM Array Shared Bit Word Lines Capacitance Management
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Solution Overview
Problem
Conventional magnetic random access memory (MRAM) arrays face challenges in efficiently writing data due to the need for sufficient current in write bit and digit lines, which can be affected by large gate-to-drain/source capacitance in transistors, leading to potential incorrect write operations during read modes.
Innovation Solution
The MRAM array architecture allows bit lines and word lines to function in both read and write modes by using selection transistors with buffering to manage capacitance, enabling common read/write operation modes without simultaneous operation, and employing segmented lines for improved control and reduced capacitance issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate write bit lines and write digit lines are used for write operations, then write current can be sufficiently provided to control magnetization direction, but the large gate-to-drain/source capacitance in selection transistors can cause inadvertent write operations during read modes and reduce writing efficiency
Solution Approach 1:
The patent merges the functions of bit lines and write bit lines, and word lines and write digit lines, allowing the same physical lines to serve both read and write operations. This is achieved by using selection transistors that can be configured through buffering to prevent inadvertent writes while enabling sufficient write current, thus eliminating the need for completely separate write lines and improving writing efficiency.
Solution Approach 2:
The patent introduces buffering as an intermediary mechanism between the control logic and the selection transistors. This buffering stage manages the gate-to-drain/source capacitance effects, preventing direct coupling that would cause inadvertent writes during read operations, while still allowing proper write current to flow when intended.
2Device complexity
If bit lines and word lines are used for both read and write operations, then device complexity is reduced, but capacitance effects from selection transistors can cause incorrect write operations during read modes
Solution Approach 1:
The buffering mechanism acts as an intermediary that decouples the control signals from the selection transistor gates during read operations. This prevents the capacitance coupling that would otherwise cause read operations to inadvertently trigger write operations, while still allowing the same physical lines to be used for both functions.
Solution Approach 2:
The selection transistors are dynamically configured through buffering to have different effective capacitance characteristics during read versus write modes. This dynamic adjustment allows the system to prevent inadvertent writes during reads while maintaining the ability to perform writes when needed, all using the same physical infrastructure.
3Reliability
If sufficient current is provided in write bit lines and write digit lines to control magnetization direction, then write reliability is improved, but the large capacitance in selection transistors can cause current leakage during read modes leading to incorrect operations
Solution Approach 1:
The buffering mechanism serves as an intermediary that controls the timing and level of current flow to selection transistors. During read operations, the buffering prevents current leakage by isolating the capacitance effects, while during write operations it allows sufficient current to flow to establish the desired magnetization direction, thus eliminating the harmful capacitance-induced leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data writing efficiency by minimizing capacitance effects and preventing inadvertent write operations during reads, maintaining memory speed and accuracy.
Implementation Method 1
These lines 22 and 24 selectively carry currents and thus each selectively create a magnetic flux proximate to the magnetic tunnel junction 16. The magnetic fields induced by current flow in the lines 22 and 24 can be used to set the non-fixed direction of the magnetic vector within the magnetic tunnel junction 16.
Implementation Method 2
The differences in magnetization vector direction cause resistance variations within the element which can be measured. For example, the shifting of the magnetization vector direction can represent two different resistances or potentials, which are then read by the memory circuit as either a logic '1' or a logic '0.'
Data Source
Figure 1A~2
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AI summary
A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.