Ferroelectric Capacitor Bit Cell Nonvolatile Logic
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
The implementation of nonvolatile logic (NVL) using ferroelectric capacitors in System on Chip (SoC) designs, allowing complete power removal without losing state information, with NVL arrays dispersing throughout the logic cloud to save and restore flip-flop states efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is used to retain state information during standby power mode, then data retention is improved, but leakage current is reduced only partially and additional power supply circuitry is required
Solution Approach 1:
The patent changes the fundamental parameter of state retention from volatile (requiring continuous power) to non-volatile (retaining state without power). By using ferroelectric capacitors with hysteresis characteristics, the circuit maintains its state information through material property changes rather than continuous electrical supply, achieving zero leakage current while preserving data retention capability.
Solution Approach 2:
The patent extracts the power dependency from the state retention function. Instead of using active circuitry (shadow latch) that requires continuous power supply, the invention uses passive ferroelectric capacitors that retain state information without any power connection, completely removing the energy consumption aspect from the data retention mechanism.
2Loss of energy
If thick gate oxide transistors and high threshold voltage transistors are used in shadow latch, then leakage current is reduced, but device complexity and area overhead increase
Solution Approach 1:
The patent replaces complex, power-intensive shadow latch circuitry with simple ferroelectric capacitor structures. The ferroelectric material itself provides the retention function without requiring additional transistors or complex circuit configurations, significantly reducing device complexity and area overhead while achieving the same leakage reduction goal.
3Productivity
If continuous power is provided to logic circuits, then system performance is maintained, but energy consumption increases for battery-operated devices
Solution Approach 1:
The patent performs preliminary action by storing the state information in ferroelectric capacitors before power removal. This allows the system to be completely powered down without losing operational state, enabling zero energy consumption during standby while maintaining the ability to rapidly restore full system performance when power is reapplied.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables zero leakage in sleep mode and rapid system state restoration, reducing energy consumption and eliminating the need for constant power sources, ideal for energy harvesting applications and handheld devices with limited resources.
Implementation Method 1
Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line
Implementation Method 2
A clamping circuit is coupled to the node Q and is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed
Data Source
AI summary
A system on chip (SoC) provides a memory array of nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit is coupled to the node Q and is operable to clamp the node Q to a voltage approximately equal to first voltage while the bit cell is not being accessed.