Dual Port Memory Interface Conversion Unit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional dual port memory devices are limited in their ability to operate with processors having different memory interfaces, such as SRAM, PSRAM, and SDRAM, due to differences in memory cell structures and interface types, leading to increased manufacturing costs and restricted accessibility in portable communication terminals.
Innovation Solution
A dual port memory device with a converting unit that transforms address and control signals from one memory interface type to another, allowing access via both SRAM and SDRAM interfaces, utilizing a DRAM memory array and including a signal converter to extract and generate appropriate signals for read, write, and refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dual port memory device uses a single memory interface type (either SRAM or SDRAM), then the manufacturing process is simplified and costs are reduced, but the device cannot be accessed by processors with different memory interface types
Solution Approach 1:
The patent introduces a converting unit as an intermediary component between the SDRAM interface and the memory array. This converting unit translates SDRAM interface signals into SRAM-compatible signals, enabling the memory device to be accessed by both SDRAM and SRAM processors through a single unified interface structure.
2Adaptability or versatility
If SRAM memory cells are used to support SRAM interface access, then processors with SRAM external bus interface can access the memory, but the layout area size increases due to the six-transistor latch structure
Solution Approach 1:
The patent creates a signal-level copy or translation layer through the converting unit. Instead of physically implementing SRAM memory cells, the converting unit replicates the SRAM interface signal behavior by translating SDRAM signals into SRAM-compatible signals, achieving SRAM interface compatibility without the area overhead of actual SRAM cells.
3Adaptability or versatility
If external bus interfaces for different memory types are used, then processors with different interfaces can access memory, but data transmission rate decreases and system performance deteriorates compared to dual port memory
Solution Approach 1:
The patent merges the functionality of multiple memory interfaces into a single unified memory device. By integrating both SDRAM and SRAM interface capabilities through the converting unit, the system eliminates the need for separate memory devices and external bus interfaces, thereby maintaining high data transmission rates and system performance while supporting multiple interface types.
4Adaptability or versatility
If a converting unit is added to support multiple memory interfaces, then processors with different interfaces can access the memory device, but the device complexity increases
Solution Approach 1:
The patent segments the memory interface functionality into distinct modules: the SDRAM interface unit, the converting unit with its address extraction and signal generation components, and the memory array. This segmentation allows each component to be optimized independently while working together as an integrated system, managing complexity through modular design.
Data Source
AI summary
A dual port memory device converts an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface, to access a memory array. The dual port memory device accesses a memory array based on an address and a control signal which are inputted via a second port and conform to the second type memory interface. The dual port memory device accesses a memory array according to the first type memory interface or the second type memory interface in response to a selecting signal. Therefore, the dual port memory device can be coupled to a processor with a first interface (e.g., PSRAM or SRAM interface) and a processor with a second interface (e.g., SDRAM interface).