Multi-chip Memory Command Control via History Tracking
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in integrating multiple chips into a single package while maintaining operational consistency and efficiency, particularly in responding to commands without addresses, which can lead to interference and unclear suspend-resume operations.
Innovation Solution
A multi-chip memory device configuration where two memory chips share input/output signal lines, with each chip determining command execution based on command history, using a chip selector, command tracker, and output enable controller to manage status read, suspend, and resume commands, and maintaining output terminals in high impedance when not selected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are integrated into a single package to increase capacity, then the storage capacity and functionality are improved, but interference between chips and control complexity increase
Solution Approach 1:
The patent divides the multi-chip system into independently controllable segments by introducing chip-specific control logic. Each memory chip is assigned a unique chip address, and the control system segments command processing by routing commands to specific chips based on their addresses, thereby managing complexity while maintaining high capacity
Solution Approach 2:
The patent introduces intermediary control components including a chip selector and command tracker that mediate between the external controller and multiple memory chips. These intermediaries manage command distribution, track command histories for each chip, and coordinate status reads, preventing interference while enabling complex multi-chip operations
2Area of stationary object
If multiple chips share input/output signal lines to reduce package size, then the package area is reduced, but signal interference and control ambiguity increase
Solution Approach 1:
The patent segments the shared I/O signal lines by introducing chip address identification. Although physical signal lines are shared, the system creates logical separation by assigning unique chip addresses to each chip, allowing the external controller to address and communicate with specific chips without interference through the shared medium
Solution Approach 2:
The patent implements preliminary chip selection through address decoding before data transmission. The chip selector receives chip address signals in advance and pre-configures the connection state of each chip, ensuring that only the intended chip responds to subsequent commands on the shared I/O lines, thereby preventing signal interference
3Speed
If chips respond to status read commands without addresses to simplify control, then command execution speed is improved, but chip identification and status retrieval become ambiguous
Solution Approach 1:
The patent performs preliminary chip selection by embedding chip address information in earlier commands or initialization sequences. The command tracker records which chip was last selected or is currently active, so when a status read command arrives without an address, the system knows which chip to query based on the previously established context, maintaining both speed and identification accuracy
Solution Approach 2:
The patent implements feedback mechanisms where the command tracker monitors and records the state of each chip and the sequence of commands issued. This feedback information is used to determine which chip should respond to address-less status read commands, ensuring that the correct chip's status is retrieved without requiring explicit addressing at every step
4Ease of operation
If suspend and resume commands are implemented without addresses to simplify operation, then ease of operation is improved, but operation ambiguity and control errors increase
Solution Approach 1:
The patent establishes preliminary chip context before suspend-resume operations by tracking which chip is currently active or has been recently addressed. When suspend or resume commands are received without addresses, the command tracker uses the previously stored chip identification information to determine the correct target chip, enabling simple operation while maintaining reliable chip-specific control
Solution Approach 2:
The patent uses feedback from the command tracker that monitors the sequence of commands and maintains state information for each chip. This feedback mechanism ensures that suspend and resume commands are correctly associated with the intended chip based on the operational history, preventing control errors while keeping the interface simple for the external controller
Data Source
AI summary
A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines whether to execute a command unaccompanied by an address, by referring to a history of commands.