DRAM Refresh Control Circuit for Row Hammer Attack Mitigation
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Solution Overview
Problem
Row Hammer attacks in DRAM cause unnecessary data loss and resource wastage due to the general refresh operation, which refreshes irrelevant Word Lines (WLs) during hammer refresh, leading to reduced memory performance.
Innovation Solution
A refresh control circuit and method that differentiates between general and hammer refresh operations by using specific block and row decoding signals to selectively refresh only the affected data block, reducing the number of irrelevant WLs refreshed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If general refresh operation is used for hammer refresh, then victim WLs can be refreshed to recover affected data, but irrelevant WLs are additionally refreshed causing resource waste and reduced memory performance
Solution Approach 1:
The memory array is divided into multiple data blocks, and the block decoding circuit selectively activates only the specific data block containing the victim WL that needs refresh, rather than refreshing all data blocks. This segmentation allows targeted refresh of affected areas while leaving other blocks untouched, thus recovering data reliability without wasting resources on irrelevant WLs.
Solution Approach 2:
The refresh operation is localized to only the affected victim WL within a specific data block, rather than applying uniform refresh to all WLs across all blocks. The block decoding circuit and row decoding circuit work together to precisely target the local region needing refresh, improving memory performance by avoiding unnecessary refresh of healthy data in other blocks.
2Reliability
If general refresh operation is used for hammer refresh, then all WLs in selected blocks are refreshed, but this causes waste of refresh current and power consumption
Solution Approach 1:
The harmful practice of refreshing irrelevant WLs is extracted and eliminated from the hammer refresh process. By using block decoding to select only the specific data block containing victim WLs, the system extracts and removes the unnecessary refresh operations on unrelated WLs, thereby reducing refresh current and power consumption while maintaining data integrity for the affected blocks.
3Reliability
If general refresh operation is used for hammer refresh, then refresh can be performed systematically, but the number of refreshed WLs exceeds the actual need reducing efficiency
Solution Approach 1:
The refresh operation transitions from a static, uniform approach (refreshing all WLs in selected blocks) to a dynamic, adaptive approach where the block decoding circuit adjusts the selection based on the specific victim WL address. This dynamic targeting ensures refresh coverage is precisely matched to actual needs, reducing the time spent refreshing unnecessary WLs while maintaining reliability for affected data.
Data Source
AI summary
A refresh control circuit includes the following: an address output circuit configured to output a to-be-refreshed address signal including a block address signal and a row address signal; a block decoding circuit configured to: receive the block address signal; decode the block address signal and output a first block selection signal for selecting multiple data blocks from the memory array, in response to that the memory array is subjected to no row hammer attack, or decode the block address signal and output a second block selection signal for selecting one data block from the memory array, in response to that the memory array is subjected to a row hammer attack; and a row decoding circuit, configured to receive the row address signal, decode the row address signal and output a row selection signal.