Peripheral Memory Bit String Accumulation Using Posit Format
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Solution Overview
Problem
Current computing systems face limitations in memory resources, leading to rounding errors and reduced accuracy in recursive operations due to finite register sizes and cache constraints when using floating-point formats, especially for large bit string operands.
Innovation Solution
Implementing control circuitry that utilizes peripheral memory device circuitry to store and accumulate results of recursive operations in a posit format, allowing for higher precision and dynamic range, and reducing overflow and underflow issues, while enabling reconfigurable bit string formats for improved performance in machine learning applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If floating-point format is used for storing bit strings in memory, then compatibility with existing systems is maintained, but rounding errors occur and accuracy is reduced in recursive operations
Solution Approach 1:
The patent changes the numerical representation parameter from floating-point format to posit format. This parameter change allows for variable precision storage where the number of significant bits can be dynamically adjusted, eliminating fixed rounding errors while maintaining system compatibility through software-level format conversion.
2Measurement precision
If larger register sizes are used to store bit strings, then accuracy in recursive operations is improved, but memory resources are consumed and device complexity increases
Solution Approach 1:
The patent segments the bit string storage into two parts: a fixed-format portion stored in standard memory registers and a variable-precision portion stored in the memory array. This segmentation allows accurate recursive operations to be performed on the fixed portion while the memory array provides extended precision storage, reducing the burden on register sizes and overall device complexity.
3Reliability
If more memory resources are allocated for storing bit strings, then overflow and underflow issues are reduced, but memory capacity available for other operations is decreased
Solution Approach 1:
The patent implements dynamic precision allocation where the memory array stores bit strings with variable precision based on the specific computational requirements. The system can dynamically adjust the number of significant bits stored in the memory array, allocating more precision only when needed for specific operations while freeing up memory capacity for other uses during normal operations.
4Productivity
If traditional floating-point formats are used, then processing speed is maintained at conventional levels, but power consumption is higher and precision is limited
Solution Approach 1:
The patent extracts the precision-critical portions of bit string operations from the main processing pipeline and performs them using dedicated memory array circuitry. This extraction allows standard floating-point operations to continue at conventional speeds in the processor while high-precision operations are handled by the memory array, reducing overall power consumption by avoiding repeated high-precision calculations in the main processor.
Data Source
AI summary
Systems, apparatuses, and methods related to bit string accumulation in memory array periphery are described. Control circuitry (e.g., a processing device) may be utilized to control performance of operations using bit strings within a memory device. Results of the operations may be accumulated in circuitry peripheral to a memory array of the memory device. For instance, a method for bit string accumulation in memory array periphery can include performing a first operation using a first bit string and a second bit string and retrieving a third bit string from a memory array or a storage location located in the periphery of the memory array. The method can further include performing a second operation using the result of the first operation and the third bit string and storing the result of the second operation in the storage location located in the periphery of the memory array.