Memory Sub-Array Propagation Circuitry for Leakage Control
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Solution Overview
Problem
As memory devices shrink, increased leakage current in transistors affects bit line length and operation predictability, and existing methods for routing read data from local to global access circuitry face timing and power consumption issues, especially as the number of sub-arrays increases.
Innovation Solution
The memory device employs propagation circuitry within each sub-array access circuitry with two inputs to efficiently route read data to global access circuitry, using a control signal to determine which input to use, ensuring predictable timing and power consumption, and incorporating buffer circuits for amplification and latch circuitry for storage to manage sense amplifier enablement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If transistors are made smaller to reduce memory device size, then memory device size is reduced, but leakage current increases
Solution Approach 1:
The memory device is divided into multiple sub-arrays arranged in sub-array columns, with each sub-array having its own local access circuitry. This segmentation allows bit lines to be confined to shorter segments rather than spanning the entire memory device, reducing the impact of leakage current while maintaining small transistor sizes for compactness.
2Length of stationary object
If sub-arrays are increased to reduce bit line length, then bit line length is reduced, but data propagation complexity increases
Solution Approach 1:
Propagation circuitry is introduced as an intermediary component within each sub-array access circuitry to automatically route read data from any sub-array to the global access circuitry. This intermediary handles the complexity of data propagation, selecting appropriate paths based on which sub-array contains the target memory cell, thereby simplifying the overall system architecture while supporting multiple sub-arrays.
3Object-generated harmful factors
If multiple sub-arrays are used to reduce leakage impact, then leakage impact is reduced, but power consumption increases
Solution Approach 1:
The propagation circuitry employs selective activation based on the target sub-array location. Control signals dynamically enable only the necessary propagation paths for the current read operation, keeping other paths inactive. This periodic or conditional activation reduces overall power consumption while maintaining the ability to access any sub-array in the column.
Data Source
AI summary
A memory device and method of operating such a device are provided. The memory device has a plurality of sub-arrays arranged to form at least one sub-array column having a first end and a second end, with each sub-array comprising a plurality of memory cells arranged in a plurality of memory cell rows and at least one memory cell column. Sub-array access circuitry is associated with each sub-array, for detecting read data from a selected memory cell column of the associated sub-array during a read operation, and global access circuitry then interfaces with the first end of the sub-array column. Each sub-array access circuitry comprises propagation circuitry for producing an output read data value, the propagation circuitry having a first input for receiving the read data detected from the associated sub-array during a read operation and a second input for receiving an output read data value produced by a linked sub-array access circuitry associated with a sub-array nearer the second end of the sub-array column. The propagation circuitry receives a control signal for identifying which of its first or second inputs should be used to produce the output read data value. As a result, an output read data value produced by any sub-array access circuitry is propagated to the global access circuitry via any linked sub-array access circuitry in the sub-array column between that sub-array access circuitry and the global access circuitry. This provides a particularly simple technique for propagating the read data value to the global access circuitry, which has both predictable timing, and consumes low power.