Variable Resistance Patterns for Leakage Current Isolation in Semiconductor Memory
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Solution Overview
Problem
Semiconductor devices face challenges in preventing defects such as leakage current, which can disrupt the normal operation of memory cells and increase overall power consumption.
Innovation Solution
The semiconductor device incorporates a plurality of first variable resistance patterns connected in series with memory cells, allowing for the identification and isolation of defective memory cells by switching the resistance pattern to a high resistance state, thereby blocking electrical connections and preventing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are connected in a cross-point array without additional isolation elements, then device complexity is reduced, but leakage current from defective cells cannot be blocked
Solution Approach 1:
A variable resistance pattern is introduced as an intermediary element between the memory cell and the bit line. This pattern can be switched between low resistance and high resistance states to control current flow. When a memory cell is defective, the variable resistance pattern switches to high resistance state to block leakage current, while maintaining the basic cross-point array structure for non-defective cells.
2Loss of energy
If all memory cells operate simultaneously without defect detection, then productivity is maintained, but defective cells cause leakage current that increases power consumption
Solution Approach 1:
The system implements a feedback mechanism where the operation state of each memory cell is detected, and based on the detection result, the variable resistance pattern is switched to appropriate resistance state. This feedback loop allows the system to identify defective cells and block their leakage current while maintaining normal operation of healthy cells, thus reducing overall power consumption without significantly impacting productivity.
3Reliability
If variable resistance patterns are added to each memory cell, then leakage current can be blocked, but device complexity increases
Solution Approach 1:
The variable resistance pattern is merged with the existing bit line structure of the cross-point array. Instead of adding completely separate isolation elements, the variable resistance pattern shares the bit line infrastructure, reducing the increase in device complexity while still achieving the function of blocking leakage current when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents the negative effects of defective memory cells by isolating them and maintaining normal operation characteristics in semiconductor devices, thereby improving overall performance and reducing power consumption.
Implementation Method 1
performing a reset operation to allow a first variable resistance pattern that is coupled to the defective memory cell to exhibit a high resistance state to block an electrical connection to the defective memory cell
Data Source
AI summary
A semiconductor device is provided to include first conductive lines extending in a first direction; a second conductive lines disposed to be spaced apart from the first conductive lines in a third direction and extending in a second direction intersecting with the first direction; a memory cells overlapping with intersection areas of the first conductive lines and the second conductive lines; and first variable resistance patterns that are respectively coupled in series to the memory cells, one first variable resistance pattern per memory cell, so that each first variable resistance pattern and a corresponding memory cell are connected between a corresponding first conductive line of the first conductive lines and a corresponding second conductive line of the second conductive lines.