Memory Device Fly Word Line Power Reduction
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Solution Overview
Problem
Conventional memory devices experience unnecessary power consumption due to dummy read and write operations, where entire rows of memory cells are activated during read/write operations, leading to inefficiency.
Innovation Solution
The implementation of a memory device with a dual-word line system, where each row includes a regular word line and a fly word line, allowing selective activation of memory cells, reducing the number of cells in dummy read situations by using 2-to-1 multiplexers instead of N-to-1 multiplexers, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If entire rows of memory cells are activated during read/write operations, then data access is simplified, but power consumption increases due to dummy read and write operations
Solution Approach 1:
The patent divides each row of memory cells into two separate segments, each controlled by its own word line. This segmentation allows selective activation of only the necessary memory cell segment during read/write operations, preventing dummy operations on the other segment and thereby reducing power consumption while maintaining simplified data access through the dual-word line control mechanism
Solution Approach 2:
Instead of activating entire rows of memory cells during read/write operations, the patent enables partial action by activating only the specific segment (half of the row) that contains the target data. This partial activation eliminates unnecessary power consumption from dummy operations on the non-target segment while still achieving complete data access capability
2Loss of energy
If 2-to-1 multiplexers are used instead of N-to-1 multiplexers, then the number of memory cells in dummy read situations is reduced, but device complexity increases
Solution Approach 1:
The patent segments the memory array into two portions along a first dimension and two portions along a second dimension, creating four quadrants. Each quadrant is controlled by a combination of first and second word lines, enabling the use of 2-to-1 multiplexers instead of N-to-1 multiplexers. This segmentation reduces power consumption by eliminating dummy reads while managing complexity through systematic segmentation
3Use of energy by moving object
If memory array is divided into multiple portions controlled by different word lines, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent divides the memory array into four distinct portions by segmenting along two perpendicular dimensions, with each portion controlled by a specific combination of first and second word lines. This two-dimensional segmentation strategy reduces power consumption through selective activation while organizing the control system in a structured manner that manages complexity
Solution Approach 2:
The patent introduces a second dimension of segmentation perpendicular to the first dimension, creating a two-dimensional grid of memory cell portions. This dimensional approach allows for more efficient power management through selective row/column activation patterns while providing a systematic framework for controlling the increased number of segments
Data Source
AI summary
A memory device includes a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns. A first word line is connected to a first plurality of the memory cells of a first row of the array, and a second word line is connected to a second plurality of the memory cells of the first row of the array. In some examples, the plurality of memory cells are arranged in or on a substrate, and the first word line is formed in a first layer of the substrate and the second word line is formed in a second layer of the substrate.