Semiconductor Memory Repair Circuit for Test Time Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices require extended test times due to the need to enable only a redundancy column line after a repair operation, rather than simultaneously testing with double column lines, which prolongs the overall test operation duration.
Innovation Solution
A semiconductor memory device with a repair circuit that includes a column repair signal generation block for comparing input addresses with first and second repair addresses, enabling column repair signals to access either a normal column line or a redundancy column line, allowing for simultaneous testing with double column lines post-repair operation by inverting the most significant bit of repair addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If only a redundancy column line is enabled after a repair operation, then the defective memory cell is repaired, but the test operation duration is prolonged
Solution Approach 1:
The patent implements dynamic operation mode switching between normal mode and test mode. In normal mode, only the redundancy column line is enabled for repaired addresses. In test mode, both normal and redundancy column lines are simultaneously enabled, allowing parallel testing. This dynamic adjustment of system behavior based on operational context resolves the contradiction between ensuring repair reliability and minimizing test time.
Solution Approach 2:
The patent segments the column line operation into two independent paths: normal column lines and redundancy column lines. By generating separate column select signals (NYI1, NYI2 for normal lines; RYI for redundancy lines) and enabling them independently based on operational mode, the system can simultaneously activate both paths during testing while maintaining the traditional single-path operation during normal functionality, thus reducing test duration without affecting repair capability.
2Loss of time
If double column lines are tested simultaneously after repair, then test operation time is reduced, but the complexity of control signals increases
Solution Approach 1:
The patent prepares both normal and redundancy column select signal generation paths in advance, with all necessary decoding logic and signal routing pre-configured. During test mode, the system simply activates both paths simultaneously using pre-established control mechanisms (mode control signal TM_DB), avoiding the need for complex real-time coordination. This preliminary preparation of signal paths reduces the actual test time while keeping the control complexity manageable through systematic signal design.
3Adaptability or versatility
If the most significant bit of repair address is inverted to generate second repair address, then additional normal column line can be accessed, but the decoding logic complexity increases
Solution Approach 1:
The patent extends the address decoding from a single-dimension approach (direct address matching) to a two-dimension approach by incorporating bit inversion. The second repair address is generated by inverting the most significant bit of the first repair address, creating an additional address dimension. This allows the system to access a broader range of column lines (both normal and redundancy) while maintaining structured decoding logic through systematic bit manipulation rather than requiring completely new decoding pathways.
Data Source
AI summary
A repair circuit includes a column repair signal generation block suitable for comparing an input address with respective first and second repair addresses in response to a mode control signal, and generating first and second column repair signals; a normal decoder suitable for accessing any one of a first normal column line corresponding to the input address and a second normal column line corresponding to an address that is different in terms of a most significant bit from the input address, in response to the first and second column repair signals; and a redundancy decoder suitable for decoding the first repair address in response to the first and second column repair signals, wherein the second repair address is generated by inverting a most significant bit of the first repair signal.