Adaptive Semi-Circle Select Gate Bias for NAND Memory
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Solution Overview
Problem
Semi-circle drain side select gate (SC-SGD) memory technology faces inefficiencies due to etching variations, leading to charge migration and difficulties in selecting biases for drain side select gates, resulting in inconsistent threshold voltage distributions and potential NAND string cut-off.
Innovation Solution
A memory apparatus and method that determine a unique select gate voltage for each grouping of memory cells, applying it to turn on the drain-side select gate transistors, thereby adapting to individual transistor threshold voltages and minimizing downshift risks through adaptive select gate bias searching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If etching technology is used to create semi-circular memory holes, then die size is reduced, but charge migration occurs and threshold voltage distribution becomes inconsistent
Solution Approach 1:
The patent applies different select gate voltages to different blocks of memory cells based on their specific etching characteristics and charge migration patterns. Each block is characterized to determine its unique threshold voltage distribution, and local quality adjustments are made by applying tailored voltage biases to compensate for etching-induced variations in different regions of the memory device.
Solution Approach 2:
The patent changes the select gate voltage parameter dynamically based on block characteristics. By measuring and characterizing each block's threshold voltage distribution, the system adjusts the select gate voltage parameter to optimize performance for that specific block, thereby compensating for etching variations and maintaining consistent threshold voltage distribution across the entire memory device.
2Device complexity
If a single select gate voltage is applied to all memory blocks, then device complexity is reduced, but NAND string cut-off occurs due to etching variations
Solution Approach 1:
The patent segments the memory device into multiple blocks, each with its own characterized threshold voltage distribution. By dividing the memory space into manageable segments and applying individualized select gate voltages to each segment, the system achieves reliable NAND string selection without requiring overly complex global control mechanisms.
Solution Approach 2:
The patent performs preliminary characterization of each block's threshold voltage distribution before normal operation. This preliminary action captures the etching-induced variations in each block, enabling the system to pre-determine appropriate select gate voltages for each block, thereby preventing NAND string cut-off during subsequent read and program operations.
3Reliability
If higher select gate voltage is applied to compensate for charge migration, then threshold voltage consistency improves, but energy consumption increases
Solution Approach 1:
The patent optimizes the select gate voltage parameter for each block based on its specific characteristics, applying the minimum necessary voltage to achieve consistent threshold voltage distribution. By characterizing each block and determining its optimal voltage requirement, the system avoids unnecessary energy consumption while maintaining reliability.
Solution Approach 2:
The patent applies localized voltage adjustments only where needed to compensate for charge migration effects. Rather than applying uniformly high voltages across the entire memory device, the system tailors voltage application to specific blocks that require compensation, thereby reducing overall energy consumption while maintaining threshold voltage consistency.
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. Each of the strings has a drain-side select gate transistor on a drain-side connected to one of a plurality of bit lines. A control means is coupled to the word lines and the plurality of bit lines and the drain-side select gate transistors. The control means determines a unique select gate voltage for each of a plurality of groupings of the memory cells that is individually adapted for each of the plurality of groupings. The control means then applies the unique select gate voltage to the drain-side select gate transistor of selected ones of the strings of each of the plurality of groupings of the memory cells to turn on the drain-side select gate transistor of the selected ones of the strings during a memory operation.