Read-Only Memories TRIZ Cases

Differentiated pass voltages applied to selected and unselected sub-blocks suppress threshold voltage increases in unselected memory cells.

A memory controller selects first and second shift patterns via index information to generate optimal read voltages for nonvolatile memory cells.

A block closure technique merges cell voltage distribution parameters across multi-level cell word lines to maintain data integrity.

A memory device applies positive voltages to global select lines while grounding other lines to suppress channel boosting in unselected blocks.

A data storage apparatus uses optimal and oversampling read voltages to detect and correct potential error bits in memory cells.

A control circuit adjusts drain-side dummy word line voltage based on selected word line position to boost unselected NAND channel potential.

Well voltage compensation in a sense amplifier minimizes output variations, enhancing data accuracy despite reduced transistor dimensions.

Precharges ReRAM word and bit lines to intermediate voltages, reducing voltage swing amplitude to prevent false reads during high-density data access.

Controller separates residual data from target wordlines to resolve storage density versus alignment trade-offs, reducing read latency.

A keeper circuit shares a single long-channel NMOS transistor across multiple bitlines to maintain precharge voltages.

Floating the control gate driver output for retired sectors prevents current paths that lower supply voltage and cause read failures.

Continuous scanning time-domain sensing applies a ramp voltage to word lines for parallel multi-level memory cell threshold detection.

Pre-charge circuitry initializes the output capacitor to supply voltage, reducing power consumption and current losses during ramp-phase.

A semiconductor memory sense circuit adjusts pull-up current values based on write data to increase threshold distribution margins.

Unique select gate voltages adapt to etching variations, minimizing threshold voltage downshift and preventing NAND string cut-off.

A memory control circuit unit adjusts retry-read parameter weights to prioritize effective correction sequences.

A semiconductor memory device groups data latch circuits to enable parallel data transfer via a selection circuit.

A resistive nonvolatile memory writing method applies segmented up and down write pulse signals to establish target resistance values efficiently.

Firmware-based digital-analog converter control replaces hard-wired logic to eliminate lengthy engineering change orders for bug fixes.

A voltage regulator uses resistor elements to stabilize program voltages across semiconductor substrates.

Segmenting the circuit into dedicated program and read paths protects low voltage transistors from breakdown while enhancing operation speed.

Grouping read program units with shared signal tracks reduces parasitic capacitance interference in NAND flash memory layouts.

A nonvolatile memory device performs cell counting to adjust read voltages for accurate data retrieval.

A control circuit applies dynamic read voltages to identify storage states in rewritable non-volatile memory cells.

A processing device verifies read voltage levels to detect defective storage units in memory dice.

Selective erase verify operations reduce peak current and power consumption while maintaining threshold voltage control accuracy.

A non-volatile memory system dynamically adjusts soft program verify voltage levels to optimize erase performance across different block usage patterns.

Source side injection programs SRAM data into non-volatile storage using thin gate insulating films, enabling high-speed operation at low power supply voltages.

A non-volatile static random access memory device uses programmable resistive devices to store multiple logic states within each memory cell.

A 2Plane programming method writes data and backup copies simultaneously into separate memory planes.

A flash memory controller tests various clock frequencies to identify suitable signals for variable-frequency operation.

A memory device uses dedicated pads to receive external ROM data and clock signals for test mode operations.

A nonvolatile memory cell uses a switching unit to compare cell current with a reference value during programming operations.

A redundancy repair apparatus generates a compact code from extra fuse signals to select replacement blocks in memory arrays.

A storage controller shapes write data into fewer states before encoding and writing to nonvolatile memory cells.

Periodic switching of a p-channel MOS transistor reduces gate insulating film stress and improves row decoder reliability in NAND flash memory.

A nonvolatile memory device migrates read data to a second address region based on read time comparisons.

A read voltage update engine adjusts thresholds based on error type counts to improve data accuracy in non-volatile memory.