Semiconductor Memory Device Selective Erase Verify
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in erase operations due to high peak currents and power consumption during pre-read and erase verify operations, which can result in increased power consumption and potential errors in threshold voltage control.
Innovation Solution
The semiconductor memory device employs a method where a pre-read operation is performed on only selected memory transistors, and an erase verify operation is conducted without pre-reads on others, reducing unnecessary current flow and optimizing voltage application to manage threshold voltages effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-read and erase verify operations are performed on all memory transistors, then data accuracy is maintained, but peak current and power consumption increase
Solution Approach 1:
The patent divides the memory block into multiple segments and performs erase verify operations selectively on specific segments rather than all segments. This segmentation allows the system to maintain data accuracy for critical segments while reducing power consumption by skipping verify operations on less critical segments.
Solution Approach 2:
The patent applies partial action by performing erase verify operations on only a portion of the memory transistors (specific segments) rather than all transistors. This partial verification approach reduces peak current and power consumption while maintaining sufficient data reliability through targeted verification of critical data portions.
2Manufacturing precision
If pre-read operation is performed on all memory transistors, then threshold voltage control accuracy is improved, but peak current increases
Solution Approach 1:
The patent applies local quality by performing pre-read operations selectively on specific segments or regions of the memory block rather than uniformly across all memory transistors. This allows threshold voltage control accuracy to be maintained in critical local regions while reducing peak current by omitting pre-read operations in less critical regions.
Data Source
AI summary
A semiconductor memory device includes first and second bit lines, first and second memory transistors connected to the respective first and second bit lines, a source line connected to the first and second memory transistors, and a word line connected to gate electrodes of the first and second memory transistors. In an erase operation that erases data in the first and second memory transistors: a first erase voltage application operation is performed; an erase verify operation is performed on only one of the first and second memory transistors; and a second erase voltage application operation is performed without performing the erase verify operation on another of the first and second memory transistors.