Read Voltage-Assisted Memory Sub-System Manufacturing Tests
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Solution Overview
Problem
Conventional memory sub-system manufacturing tests are time-consuming and inefficient, as they often require testing bit error rates at multiple read voltage levels corresponding to varying write-to-read delays, which can delay shipment and potentially miss defects if only static bit error rates are tested.
Innovation Solution
A staged approach to manufacturing testing that verifies read voltage levels and selects initial read voltage levels achieving low bit error rates at shortest write-to-read delays, allowing for efficient detection of defective storage units and reducing unnecessary testing by skipping tests at longer delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manufacturing tests are performed at multiple read voltage levels corresponding to varying write-to-read delays, then memory quality and reliability are improved, but testing time and manufacturing duration increase
Solution Approach 1:
The patent applies preliminary action by first verifying read voltage levels and selecting initial read voltage levels that achieve low bit error rates at shortest write-to-read delays before proceeding to test at longer delays. This preliminary screening identifies defective storage units early, allowing the testing process to skip unnecessary tests at longer delays for units that pass the initial check, thereby reducing overall testing time while maintaining reliability.
Solution Approach 2:
The patent segments the manufacturing test into distinct stages: first verifying read voltage levels, then selecting initial read voltage levels for testing at shortest delays, and finally skipping tests at longer delays for units that pass initial testing. This segmentation allows the testing process to be divided into manageable phases that can be executed efficiently, reducing total testing duration while ensuring quality.
2Loss of time
If static bit error rates are tested only at fixed read voltage levels, then testing time is reduced, but defective storage units may be missed
Solution Approach 1:
The patent applies dynamics by transitioning from static testing at fixed read voltage levels to dynamic testing that adapts to varying write-to-read delays. The system dynamically selects read voltage levels based on the actual delay characteristics of each storage unit, ensuring that defective units are detected while avoiding unnecessary tests. This dynamic approach maintains high reliability without significantly increasing testing time.
Solution Approach 2:
The patent changes the testing parameters by using variable read voltage levels instead of fixed levels, and by adjusting the testing sequence based on write-to-read delay characteristics. This parameter change allows the testing process to adapt to different storage unit characteristics, improving defect detection while controlling testing time through intelligent parameter selection.
3Reliability
If all storage units are tested at all read voltage levels, then comprehensive quality verification is achieved, but manufacturing productivity decreases
Solution Approach 1:
The patent applies the skipping principle by allowing the testing process to skip tests at longer write-to-read delays for storage units that pass the initial testing at shortest delays. This selective skipping maintains comprehensive quality verification for units that require it while rushing through the testing process for units that clearly pass initial checks, thereby improving manufacturing productivity without sacrificing reliability.
Solution Approach 2:
The patent applies partial action by testing only the necessary read voltage levels for each storage unit based on its performance at shortest delays. Instead of universally testing all units at all voltage levels, the system applies testing selectively - performing full verification only when necessary, and skipping unnecessary tests for units that demonstrate adequate performance initially, thus balancing quality verification with manufacturing throughput.
Data Source
AI summary
A system includes memory dice, each having a register to store multiple read voltage levels. A processing device is to test each memory die by verification, via access to the multiple read voltage levels, whether each read voltage level falls within a corresponding relative voltage range. The processing device selects an initial read voltage level that achieves bit error rates not satisfying a threshold criterion at one of a first or a second shortest write-to-read (W2R) delay for the memory die and determines a bit error rate, using the initial read voltage level, of storage units of the memory die. The processing device reports the memory die as defective in response to one of: (i) a read voltage level, of the multiple read voltage levels, failing to verify; or (ii) the bit error rate of one or more storage units of the memory die satisfying the threshold criterion.