ReRAM Read Method Precharging Word Bit Lines
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Solution Overview
Problem
High-density resistive random access memory (ReRAM) devices face challenges in read performance due to increased capacity and resistance of word and bit lines, leading to longer transition times for charge or discharge, which deteriorates read performance and can result in false reads or erases.
Innovation Solution
A method and device for reading data from ReRAM that involves precharging word and bit lines to intermediate voltages before applying a read voltage to the selected lines, reducing voltage amplitudes and preventing unexpected potential differences, allowing for efficient data reading without altering the memory cell state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged at intersections of column selecting lines and row selecting lines to achieve high-density ReRAM, then manufacturing cost is reduced and density is improved, but voltage transitions on word lines and bit lines become slower due to increased capacity and resistance
Solution Approach 1:
The patent applies preliminary action by precharging the selected word line and selected bit line to intermediate voltages (e.g., Vread/2 and Vbl_read/2) before the actual read operation. This preliminary voltage application reduces the voltage transition time during the read operation by limiting the voltage swing amplitude, thereby resolving the speed degradation caused by high-density cell arrangement.
2Ease of manufacture
If high-density ReRAM is implemented with increased word line and bit line capacity, then manufacturing cost decreases, but read performance deteriorates due to longer charge/discharge transition times
Solution Approach 1:
The patent precharges the selected word line to an intermediate voltage (Vread/2) and the selected bit line to an intermediate voltage (Vbl_read/2) before performing the read operation. This preliminary action reduces the voltage swing amplitude during reading, thereby reducing charge/discharge transition times and preventing false reads or erases, thus maintaining read performance in high-density configurations.
3Speed
If voltage amplitude is increased to improve read speed, then reading performance improves, but false reads and erases occur due to unexpected potential differences
Solution Approach 1:
The patent applies preliminary precharging to intermediate voltages to establish a controlled initial state before the read operation. This prevents unexpected potential differences by ensuring that the selected word line and bit line start from known intermediate voltage levels, thereby avoiding false reads and erases while maintaining adequate read speed.
Solution Approach 2:
The patent changes the voltage parameters by using intermediate voltages (Vread/2 and Vbl_read/2) for precharging instead of full read voltages. This parameter modification reduces the voltage swing amplitude during the read operation, preventing data integrity issues while maintaining sufficient read speed through controlled voltage transitions.
Data Source
AI summary
The present invention provides a method of reading data from a non-volatile memory device including word lines and bit lines that intersect each other and electrically rewritable memory cells that are arranged at intersections of the word lines and the bit lines and that respectively have variable resistive elements nonvolatily storing a resistances as data. The method includes: precharging a selected word line and unselected word lines to a first word line voltage and a selected bit line and unselected bit lines to a first bit line voltage; and reading data from a memory cell connected to the selected word line and the selected bit line by changing the voltage of the selected word line from the first word line voltage to a second word line voltage and changing the voltage of the selected bit line from the first bit line voltage to a second bit line voltage after the precharging.