Dynamic Retry-Read Parameter Sequencing in Flash Memory

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Solution Overview

Problem

The existing memory retry-read methods for flash memory modules are inefficient due to the fixed sequence of retry-read parameters, which leads to increased time spent on retry-read operations, especially when lower-ranked effective retry-read parameters are chosen first, resulting in prolonged data correction times.

Innovation Solution

A memory retry-read method that dynamically adjusts the sequence of retry-read parameter groups based on their weights, allowing for immediate prioritization of effective retry-read parameters by adjusting the weights of available retry-read parameter groups after successful corrections, thereby reducing the time required for subsequent retry-read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a fixed sequence of retry-read parameters is used, then the retry-read operation can be executed with simple control logic, but the time required for retry-read operations increases when lower-ranked effective parameters are chosen first

Engineering Contradiction:
Improvecontrol logic simplicityVSAvoidretry-read operation time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the retry-read parameter sequence adjustable rather than fixed. The controller dynamically resequences the retry-read parameters based on their effectiveness in correcting erroneous bits, allowing the system to adapt to different error patterns and memory conditions, thereby reducing the time required for retry-read operations while maintaining manageable control logic through automated resequencing.

Inventive Principle:
Principle #15Dynamics

2Productivity

If retry-read parameters are selected in a fixed priority sequence, then the selection process is simple and deterministic, but effective parameters lower in the sequence cause prolonged data correction times

Engineering Contradiction:
Improvedata correction efficiencyVSAvoidtime spent on retry-read operations
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements feedback by monitoring the effectiveness of each retry-read parameter in correcting erroneous bits and using this information to resequence subsequent retry-read parameters. The controller analyzes which parameters successfully correct errors and prioritizes them in future retry-read operations, creating a feedback loop that continuously optimizes the parameter selection sequence to improve data correction efficiency and reduce operation time.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies preliminary action by pre-establishing multiple retry-read parameter sequences with different priorities before actual read operations occur. When retry-read is needed, the controller can quickly switch between pre-defined sequences based on the detected error patterns, avoiding the need for complex real-time analysis while still prioritizing the most effective parameters for rapid data correction.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If multiple retry-read parameters are tested before finding an effective one, then more correction options are available, but the number of retry-read operations increases

Engineering Contradiction:
Improvedata correction capabilityVSAvoidretry-read operation count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by modifying the priority ordering of retry-read parameters based on their demonstrated effectiveness. Instead of testing multiple parameters in a fixed sequence, the system changes the sequence parameters dynamically, placing the most effective parameters at the beginning of the retry-read list. This reduces the number of retry operations needed while maintaining high reliability through the use of proven effective parameters.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9773565B1Memory retry-read method, memory storage device and memory control circuit unit
Publication Date: 2017.09.26 PHISON ELECTRONICS
  • US9773565B1 patent drawing
  • US9773565B1 patent drawing
  • US9773565B1 patent drawing

AI summary

A memory retry-read method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a sequence of several retry-read parameter groups according to several weights of the retry-read parameter groups; reading data from a physical programming unit according to a read voltage; if the data are unable to be corrected by a corresponding ECC code, choosing an adjustment retry-read parameter group from the retry-read parameter groups; retrying reading new data from the physical programming unit according to the adjustment retry-read parameter group; if the new data are able to be corrected by the corresponding ECC code, determining the adjustment retry-read parameter group to be an available retry-read parameter group; and adjusting the weight of the available retry-read parameter group.