Semiconductor Memory Device Data Latch Grouping for Power Reduction
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently transferring data to data latch circuits, leading to high power consumption and voltage peaks due to simultaneous access of all data latch circuits connected to a common bus, which results in prolonged data input times and increased energy usage.
Innovation Solution
The semiconductor memory device divides data latch circuits into groups, allowing simultaneous data transfer from data retention circuits to multiple data latch circuits via a selection circuit, reducing power consumption and improving data write speed by accessing each group sequentially with a clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all data latch circuits connected to a common bus are accessed simultaneously, then data transfer speed is improved, but power consumption increases and voltage peaks occur
Solution Approach 1:
The patent divides data latch circuits into multiple groups (first group, second group, etc.) that are connected to different buses. Instead of accessing all latch circuits simultaneously through a single bus, the system segments them into separate groups that can be accessed in parallel through multiple buses, thereby reducing power consumption and avoiding voltage peaks while maintaining high data transfer speed.
2Speed
If all data latch circuits connected to a common bus are accessed simultaneously, then data transfer speed is improved, but instantaneous voltage peaks occur
Solution Approach 1:
The patent segments data latch circuits into multiple groups connected to different buses. By distributing the access load across multiple buses rather than concentrating it on a single common bus, the system avoids instantaneous voltage peaks that would occur when all latch circuits are accessed simultaneously through one bus, while still achieving high data transfer speed through parallel access.
3Use of energy by moving object
If data is transferred sequentially to data latch circuits, then power consumption is reduced, but data input time increases
Solution Approach 1:
The patent segments data latch circuits into multiple groups that can be accessed in parallel through different buses. This allows the system to transfer data to multiple latch circuits simultaneously rather than sequentially, significantly reducing data input time while maintaining lower power consumption compared to accessing all latch circuits through a single common bus.
Solution Approach 2:
The patent introduces an additional dimension of parallelism by using multiple buses to access different groups of data latch circuits simultaneously. This dimensional expansion from single-bus sequential access to multi-bus parallel access enables the system to reduce both power consumption and data input time by performing multiple data transfer operations at the same time.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes n (n being a natural number of 2 or more) data retention circuits connected to a data input/output terminal; n buses connected respectively to the n data retention circuits; m×n data latch circuits connected to the buses, with m (m being a natural number of 2 or more) data latch circuits being connected per one of the buses; and a selection circuit configured to simultaneously perform data transfer from/to the data retention circuits for a plurality of the data latch circuits in units of a group including the plurality of the data latch circuits, the data latch circuits being divided into the groups so that not all the data latch circuits connected to the same bus are included in the same group.