Non-volatile Memory Cell With Segmented Program And Read Paths
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Solution Overview
Problem
Conventional non-volatile memory cells face damage due to breakdown of low voltage select transistors during programming, as they cannot withstand higher program voltages, necessitating specialized bias voltage designs to reduce voltage stress.
Innovation Solution
A non-volatile memory cell array design with a first select transistor, a first floating gate transistor, a second floating gate transistor, and a second select transistor, where the second select transistor is a low voltage device with a thinner gate oxide layer, allowing for optimized programming and reading efficiencies by controlling bias voltages and active region areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a low voltage select transistor is used to achieve faster operation speed, then the operation speed is improved, but the transistor cannot withstand higher program voltage and may break down during programming
Solution Approach 1:
The memory cell is divided into two separate paths: a program path containing a medium voltage select transistor (MSG1) for programming operations, and a read path containing a low voltage select transistor (MSG2) for read operations. This segmentation allows each transistor to be optimized for its specific function without compromise.
Solution Approach 2:
Different voltage characteristics are assigned to different parts of the circuit: the program path uses medium voltage devices with thicker gate oxide layers to withstand high program voltages, while the read path uses low voltage devices with thinner gate oxide layers for faster operation. Each path has the local quality needed for its specific operation.
2Reliability
If a medium voltage select transistor is used to withstand higher program voltage, then the voltage withstand capability is improved, but the operation speed becomes slower
Solution Approach 1:
The memory cell is divided into two separate paths: a program path containing a medium voltage select transistor (MSG1) for programming operations, and a read path containing a low voltage select transistor (MSG2) for read operations. This segmentation allows each transistor to be optimized for its specific function without compromise.
Solution Approach 2:
Different voltage characteristics are assigned to different parts of the circuit: the program path uses medium voltage devices with thicker gate oxide layers to withstand high program voltages, while the read path uses low voltage devices with thinner gate oxide layers for faster operation. Each path has the local quality needed for its specific operation.
3Reliability
If specialized bias voltage designs are applied to protect the low voltage select transistor during programming, then the transistor protection is improved, but the voltage stress on the transistor is reduced and programming efficiency is compromised
Solution Approach 1:
The low voltage select transistor (MSG2) is extracted from the program path and placed only in the read path. This removes the vulnerable component from the high-stress programming operation entirely, eliminating the need for protective bias voltage designs while maintaining transistor protection.
Solution Approach 2:
Instead of protecting the low voltage transistor during programming by applying specialized bias voltages, the invention inverts the approach by assigning the low voltage transistor exclusively to read operations where it can operate at full speed without protection concerns, while programming is handled by a dedicated medium voltage transistor.
Data Source
AI summary
A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second floating gate transistor and a second select transistor. The first select transistor is connected with a program source line and a program word line. The first floating gate transistor includes a floating gate. The first floating gate transistor is connected with the first select transistor and a program bit line. The second floating gate transistor includes a floating gate. The second floating gate transistor is connected with a read source line. The second select transistor is connected with the second floating gate transistor, the read word line and the read bit line. The floating gate of the second floating gate transistor is connected with the floating gate of the first floating gate transistor.