Memory Controller Read Voltage Shift Patterns
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory systems, inappropriate read voltages lead to increased errors and latency during data retrieval, deteriorating read performance due to the need for error correction and retry operations.
Innovation Solution
A memory system with a controller that manages multiple shift patterns for read voltages, using index information to select appropriate voltage patterns for each memory cell group, reducing the number of required patterns and improving read performance by generating optimal read voltages based on first and second shift patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the read voltage is not appropriate, then errors occur in the read data, but increasing the number of read voltage patterns increases device complexity and latency
Solution Approach 1:
The patent segments the read voltage adjustment into two distinct stages: a first shift pattern that applies a coarse adjustment to the default read voltage, and a second shift pattern that applies a fine adjustment based on the first shift result. This segmentation allows the system to achieve accurate read voltages without requiring an exhaustive set of read voltage patterns, thereby reducing device complexity while maintaining reliability.
Solution Approach 2:
The patent applies the first shift pattern as a preliminary action before applying the second shift pattern. By pre-adjusting the read voltage with the first shift pattern, the system narrows down the range of possible threshold voltage variations, making the subsequent second shift pattern more effective and reducing the total number of patterns needed.
2Reliability
If error correction or retry is executed, then read data accuracy is improved, but latency increases
Solution Approach 1:
The patent performs preliminary adjustment of the read voltage using the first shift pattern before the actual read operation. This pre-adjustment reduces the likelihood of read errors, thereby reducing the need for error correction or retry operations and lowering read latency.
Solution Approach 2:
The patent uses feedback from the first shift pattern result to determine the second shift pattern. This feedback mechanism ensures that the final read voltage is optimally adjusted based on the actual threshold voltage distribution, improving read data accuracy and reducing the need for error correction.
3Productivity
If multiple read voltage patterns are managed for each memory cell group, then read performance is improved, but management complexity increases
Solution Approach 1:
The patent segments the voltage pattern management into two distinct layers: first shift patterns that are applied uniformly across memory cell groups, and second shift patterns that are selectively applied based on the first shift results. This segmentation simplifies the management complexity by reducing the number of patterns that need to be individually managed for each memory cell group.
Solution Approach 2:
The first shift pattern serves as a universal adjustment that can be applied to all memory cell groups, while the second shift pattern provides targeted fine-tuning. This multi-functionality approach allows the system to maintain high read performance without requiring separate comprehensive voltage patterns for each memory cell group.
Data Source
AI summary
A memory system includes a memory including nonvolatile memory cells, and a controller configured to set read voltages for reading data stored in the nonvolatile memory cells. The controller stores first shift patterns relating to a plurality of read voltages, first index information associating to a first shift pattern with each of a plurality of memory cell groups, second shift patterns relating to differences between read voltages and read voltages set according to a first shift pattern, and second index information associating a second shift pattern with each memory cell group. The controller generates read voltages of a target memory cell group based on the first shift pattern voltages and the second shift pattern voltages.


