Non-Volatile SRAM With Programmable Resistive Devices
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Solution Overview
Problem
Static random-access memory (SRAM) devices are limited by their high cost and low density, making them less suitable for large-scale applications compared to dynamic random-access memory (DRAM), and they lack non-volatile storage capabilities, which are essential for applications like field-programmable gate arrays (FPGAs).
Innovation Solution
A non-volatile static random-access memory (nvSRAM) device with multiple storage states is developed, utilizing programmable resistive devices that can be dynamically configured to represent logic states, allowing for the storage of multiple bits per memory cell through differential resistance values, enabling both volatile and non-volatile storage configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional SRAM is used for storage, then fast access speed and low power consumption are achieved, but high cost and low density limit large-scale applications
Solution Approach 1:
The patent merges volatile SRAM structure with non-volatile resistive memory elements, combining the fast access characteristics of SRAM with the high density and non-volatile properties of resistive memory. The six-transistor SRAM cell is integrated with programmable resistive devices to create a hybrid memory cell that achieves both speed and density.
Solution Approach 2:
The invention uses composite memory structures combining different material properties - the SRAM transistors provide switching functionality and the programmable resistive devices provide non-volatile storage. This composite approach allows the memory to leverage the strengths of both technologies while mitigating their individual weaknesses.
2Use of energy by moving object
If SRAM is used for configuration memory in FPGAs, then low power consumption and fast operation are achieved, but high cost and limited size are problems
Solution Approach 1:
The patent implements dynamic programmability where the resistive devices can be reconfigured during operation. The memory cells can switch between different resistance states programmably, allowing the FPGA configuration memory to be dynamically reprogrammed while maintaining low power operation during normal read/write cycles.
Solution Approach 2:
The invention changes the resistance parameter of the programmable resistive devices to encode configuration data. By programmably adjusting resistance values between high and low states, the memory can store multiple bits per cell while maintaining the low power characteristics of SRAM during operation.
3Duration of action of stationary object
If flash memory is used for non-volatile storage, then non-volatile capability is achieved, but slow speed and high power consumption occur
Solution Approach 1:
The patent segments the memory functionality into volatile SRAM components for fast access and non-volatile resistive components for data retention. The SRAM portion handles rapid read/write operations while the resistive portion maintains data persistence, allowing the system to achieve both speed and non-volatile capabilities simultaneously.
Solution Approach 2:
The hybrid memory cell serves multiple functions - it provides fast SRAM-like access during operation, non-volatile data retention when powered down, and reconfigurability through programmable resistance. This multi-functional design eliminates the need for separate volatile and non-volatile memory systems.
4Quantity of substance
If SRAM density is increased, then more storage capacity is achieved, but cost increases and the device becomes less competitive with DRAM
Solution Approach 1:
The patent nests multiple bits of storage within a single memory cell structure by utilizing the programmable resistance states of the resistive devices. Multiple resistance levels within each cell enable multi-bit storage without proportionally increasing the physical footprint, thereby increasing density while controlling cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nvSRAM device achieves efficient storage of multiple logic states in a compact and cost-effective manner, overcoming the limitations of traditional SRAM by providing non-volatile storage capabilities and improved density, making it suitable for applications requiring low power consumption and high speed.
Implementation Method 1
Each memory cell may include one or more programmable resistive devices having resistance values that may be dynamically programmed during a write operation to configure the memory cell to a particular logic state
Implementation Method 2
The first transistor may include a first terminal coupled to a second node, a second terminal coupled to a first programmable resistive device, and a control terminal coupled to a first word line
Implementation Method 3
The write enable circuit may be configured to activate in response to a write enable signal on the write enable line such that current flows either from the first bit line to the second bit line, or from the second bit line to the first bit line
Data Source
AI summary
Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the multi-storage state non-volatile random access memory device has two or more memory cells. Each memory cell may include one or more programmable resistive devices that may be dynamically programmed to configure the memory cell in a particular logic state.